linux-kernel - Re: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation

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Message-ID: <524EC4DC.1020708@metafoo.de>
Date:	Fri, 04 Oct 2013 15:38:36 +0200
From:	Lars-Peter Clausen <lars@...afoo.de>
To:	monstr@...str.eu
CC:	Wolfram Sang <wsa@...-dreams.de>,
	Michal Simek <michal.simek@...inx.com>,
	linux-kernel@...r.kernel.org,
	Kedareswara rao Appana <appana.durga.rao@...inx.com>,
	Kedareswara rao Appana <appanad@...inx.com>,
	Jean Delvare <khali@...ux-fr.org>,
	Peter Korsgaard <jacmet@...site.dk>, linux-i2c@...r.kernel.org,
	Richard Röjfors <richard.rojfors@...agicore.com>,
	"Steven A. Falco" <sfalco@...ris.com>
Subject: Re: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation

On 10/04/2013 03:09 PM, Michal Simek wrote:
> 
> 
> On 10/04/2013 02:12 PM, Lars-Peter Clausen wrote:
>> On 10/04/2013 01:55 PM, Wolfram Sang wrote:
>>> On Fri, Oct 04, 2013 at 11:53:49AM +0200, Michal Simek wrote:
>>>> On 10/04/2013 07:46 AM, Wolfram Sang wrote:
>>>>>
>>>>>> +	cr = xiic_getreg32(i2c, XIIC_CR_REG_OFFSET);
>>>>>> +	cr |= XIIC_CR_DIR_IS_TX_MASK;
>>>>>> +	xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, cr);
>>>>>> +
>>>>>
>>>>> Is there no need to clear the bit again when receiving?
>>>>
>>>> This bit is cleared in xiic_xfer() -> xiic_start_xfer() ->xiic_reinit()
>>>>
>>>> xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
>>>
>>> A bit implicit, but OK.
>>>
>>>>> And did
>>>>> transferring ever work if this bit was never set before?
>>>>
>>>> I really don't know. We have switched from old driver to this new mainline one
>>>> and based on our eeprom testing we have found that this bit hasn't been setup properly.
>>>>
>>>> It is described here.
>>>> http://www.xilinx.com/support/documentation/ip_documentation/axi_iic/v1_02_a/axi_iic_ds756.pdf
>>>> page 28 - step 3.
>>>>
>>>> IIC Master Transmitter with a Repeated Start
>>>> 1. Write the IIC device address to the TX_FIFO.
>>>> 2. Write data to TX_FIFO.
>>>> 3. Write to Control Register (CR) to set MSMS = 1 and TX = 1.
>>>> 4. Continue writing data to TX_FIFO.
>>>> 5. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
>>>> 6. Write to CR to set RSTA = 1.
>>>
>>> Repeated start is not happening in the driver as well, or am I
>>> overlooking something?
>>>
>>>> 7. Write IIC device address to TX_FIFO.
>>>> 8. Write all data except last byte to TX_FIFO.
>>>> 9. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
>>>> 10. Write to CR to set MSMS = 0. The IIC generates a stop condition at the end of the last byte.
>>>> 11. Write last byte of data to TX_FIFO.
>>>
>>> CCing more people who worked on the driver in the past and might have
>>> experiences
>>
>> The current version works fine here. The driver uses whats described in the
>> datasheet as "dynamic controller logic flow" and not the "standard
>> controller logic flow". The sequence Michal mentioned above is from the
>> "standard controller logic flow" section.
> 
> Does this change break "dynamic controller logic flow"?

Not sure, but I would assume that the bit is ignored in this mode. But I
don't think the patch should be applied since this step is not in the
sequence of steps that should be done.

- Lars

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