lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 9 Oct 2013 15:07:15 -0600
From:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
To:	"H. Peter Anvin" <hpa@...or.com>
Cc:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>, monstr@...str.eu,
	delicious quinoa <delicious.quinoa@...il.com>,
	Alan Tull <atull@...era.com>, Pavel Machek <pavel@...x.de>,
	Michal Simek <michal.simek@...inx.com>,
	linux-kernel@...r.kernel.org, Dinh Nguyen <dinguyen@...era.com>,
	Philip Balister <philip@...ister.org>,
	Alessandro Rubini <rubini@...dd.com>,
	Steffen Trumtrar <s.trumtrar@...gutronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Yves Vandervennet <rocket.yvanderv@...il.com>,
	Kyle Teske <kyle.teske@...com>,
	Josh Cartwright <joshc@....teric.us>,
	Nicolas Pitre <nico@...aro.org>,
	Mark Langsdorf <mark.langsdorf@...xeda.com>,
	Felipe Balbi <balbi@...com>, linux-doc@...r.kernel.org,
	Mauro Carvalho Chehab <m.chehab@...sung.com>,
	David Brown <davidb@...eaurora.org>,
	Rob Landley <rob@...dley.net>,
	"David S. Miller" <davem@...emloft.net>,
	Joe Perches <joe@...ches.com>,
	Cesar Eduardo Barros <cesarb@...arb.net>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [RFC PATCH v2 0/1] FPGA subsystem core

On Wed, Oct 09, 2013 at 01:37:05PM -0700, H. Peter Anvin wrote:

> A very common use case would be where a device contains an FPGA but is
> presented to the user as a product, often having its own device driver
> to drive the programmed device and/or additional logic.  From *that*
> point of view it would be nice if the FPGA subsystem had the capability
> for the *device driver* to trigger a firmware load request which is then
> fed to the FPGA subsystem for programming.  This would be an in-kernel
> interface, in other words.

That is sort of backwards though, how does the driver know it should
load and start fpga progamming?

The way we are working driver attach today is to program the FPGA,
under control of user space, and then do a PCI rescan, which discovers
the FPGA device and triggers driver binding of the PCI FPGA driver.

Please keep in mind that loading the wrong FPGA could permanently
destroy the system. This is why we have meta-data encoded with the
bitstream. The user space loader does some sanity checks :)

Jason
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ