[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20131011183341.GM3041@lukather>
Date: Fri, 11 Oct 2013 20:33:41 +0200
From: Maxime Ripard <maxime.ripard@...e-electrons.com>
To: Stephen Boyd <sboyd@...eaurora.org>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Emilio Lopez <emilio@...pez.com.ar>,
linux-kernel@...r.kernel.org, kevin.z.m.zh@...il.com,
sunny@...winnertech.com, shuge@...winnertech.com,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/5] clocksource: Add Allwinner SoCs HS timers driver
Hi Stephen,
On Thu, Oct 10, 2013 at 03:46:11PM -0700, Stephen Boyd wrote:
> On 10/10/13 12:13, Maxime Ripard wrote:
> > On Wed, Sep 25, 2013 at 04:16:14PM -0700, Stephen Boyd wrote:
> >> On 09/25/13 07:03, Maxime Ripard wrote:
> >>> + sun5i_clockevent.cpumask = cpumask_of(0);
> >> Can this timer interrupt any CPU or is it hardwired to CPU0? If the
> >> interrupt can go to any CPU this should be cpu_possible_mask instead.
> > I've changed the few other things you spotted, but this one making the
> > timer unusable.
> >
> > I think what happens here is that we have the A31 I've tested these
> > patches on is a quad-core SoC. As such, the device tree has 4 CPUs
> > declared. However, we don't have any SMP support for it now. So we end
> > up having 4 cpus set as possible, and only one online (the boot cpu),
> > which isn't working.
>
> Can you explain more why it isn't working? Is the timer being rejected
> in favor of another timer?
Hmm, right, I forgot it, sorry about that.
The timers actually seem to not be working at all. I get stuck at the
delay loop calibration.
I'm away from my hardware right now, so I couldn't debug it further, but
reverting to using cpumask_of(0) makes the kernel boot flawlessly.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Download attachment "signature.asc" of type "application/pgp-signature" (837 bytes)
Powered by blists - more mailing lists