linux-kernel - Re: When USB PHY framework should be used?

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Message-ID: <CAPNxggbJkXK_RhaWSfXZKFc=iy-2UmkEukCsbOUzYSmbcqmoKw@mail.gmail.com>
Date:	Mon, 14 Oct 2013 20:17:38 +0200
From:	Arokux X <arokux@...il.com>
To:	Kishon Vijay Abraham I <kishon@...com>
Cc:	peter.chen@...escale.com, Felipe Balbi <balbi@...com>,
	Alan Stern <stern@...land.harvard.edu>,
	Greg KH <gregkh@...uxfoundation.org>,
	linux-usb@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>
Subject: Re: When USB PHY framework should be used?

Dear Kishon,

On Sat, Oct 12, 2013 at 12:07 PM, Kishon Vijay Abraham I <kishon@...com> wrote:
> Hi,
>
> On Friday 11 October 2013 10:52 PM, Arokux X wrote:
>>> I think you should have a wrapper driver to EHCI/OHCI to handle this reset.
>>
>> Thank you Kishon and Peter for the quick replies. Is there any good
>> example of such a wrapper driver in the kernel already?
>
> can you explain how your IP actually looks like? Do you have separate address
> space for EHCI and OHCI? Do you have any common address space for doing some
> configuration (USB host in OMAP used to have it)? Where does PHY registers
> reside exactly?

The knowledge I have about the IP is derived from the source code of
the different kernel trees some of which were leaked and the others
released by Allwinner. I cannot really see similarities to the other
USB IPs supported by the mainline kernel since I have zero experience
with kernel development and this simple bus glue driver is going to be
my first contribution.

USB Host Controller as available in Allwinner SoCs supports EHCI and
OHCI. The address spaces of EHCI and OHCI are separate. Let the
address of the host controller be X, then EHCI is at X and OHCI is at
X+OHCI_OFFSET, where OHCI_OFFSET = 0x100.

The driver in the vendor's tree also touches the address X + 0x800 and
enables DMA burst, similar to the SAMSUNG S5P USB HOST EHCI Controller
[1].

In addition another memory location is touched to configure the PHY.
At that place two things occur [2]: "adjust PHY's magnitude and rate"
and adjusting the threshold of the disconnect. (Both are translated
from Chinese and I'm not sure whether the former is correct).

There are either two or one USB Host Controllers in a SoC. For each
controller there are EHCI and OHCI gatable clocks, one common clock
for all the PHYs and one reset bit for each PHY.

I think this is pretty much it. As you see the EHCI and OHCI parts are
almost independent from each other. The only problem is the common
reset bit which I do not know how to manage. Any help is highly
appreciated.

Best regards,
Arokux

[1] http://lxr.free-electrons.com/source/drivers/usb/host/ehci-s5p.c#L34
[2] https://github.com/arokux/linux/commit/1f271d01b8138d5a593df18a80b4129a08eac1be#diff-2fdea331a4331eca7c86f18cd2d87e72R89
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