linux-kernel - Re: [PATCH v5 13/15] clk: tegra: introduce common gen4 super clock

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Message-ID: <CAL1qeaEpemA5ekC2qzNfQKOkjAiWU3oYp4kwmdup1s1dOjAUNA@mail.gmail.com>
Date:	Fri, 18 Oct 2013 17:16:16 -0700
From:	Andrew Bresticker <abrestic@...omium.org>
To:	Peter De Schrijver <pdeschrijver@...dia.com>
Cc:	Prashant Gaikwad <pgaikwad@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>, linux-tegra@...r.kernel.org
Subject: Re: [PATCH v5 13/15] clk: tegra: introduce common gen4 super clock

Hi Peter,

> +#define PLL_BASE_LOCK BIT(27)
> +#define PLL_MISC_LOCK_ENABLE 18

I don't see these used anywhere.

> +static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
> +                                        "pll_p", "pll_p_out4", "unused",
> +                                        "unused", "pll_x", "pll_x_out0" };

nit: insert blank line here.

> +static void __init tegra_sclk_init(void __iomem *clk_base,
> +                               struct tegra_clk *tegra_clks)
> +{

Thanks,
Andrew
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