linux-kernel - Re: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr

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Date:	Mon, 28 Oct 2013 11:34:28 +0100
From:	Andreas Werner <wernerandy@....de>
To:	Ingo Molnar <mingo@...nel.org>
Cc:	Borislav Petkov <bp@...en8.de>, tglx@...utronix.de,
	mingo@...hat.com, hpa@...or.com, x86@...nel.org,
	dave@...ux.vnet.ibm.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] X86: MM: Add PAT Type write-through in combination with
 mtrr

On Mon, Oct 28, 2013 at 11:17:49AM +0100, Ingo Molnar wrote:
> 
> * Andreas Werner <wernerandy@....de> wrote:
> 
> > > IOW, you probably could use a WC buffer here too, as it would 
> > > combine the writes coming from the FPGA.
> > > 
> > > Btw, there's also mtrr_add(..., MTRR_TYPE_WRTHROUGH, ) if you 
> > > must use a WT thing. Have you tried that?
> > 
> > For reading i need to map the mmio with attributes that allow 
> > cache-line read. Therefore i use WT. For the Virtual address i use 
> > ioremap_cache in combination with this patch to get an effective 
> > memory type of "Write-Through". This allows me to read from the 
> > mmio with "PCIe burst". The write behaviour to this region do not 
> > matter.
> 
> And regular write-back cacheable isn't sufficient because the CPU 
> could do things like prefetch your range automatically?
> 
> If the reads are for packet data and not for commands, WB could 
> still be beneficial as it should allow even higher bandwidth. (For 
> non-data with real semantics WB is probably not good.)
> 
> Thanks,
> 
> 	Ingo

Yes the reads are only for packet data, the commands or configuration
registers are mapped non cachable.

I´ve tried WB, but on PCIe Tracer i could not see any burst access.
Thats the reason why i have created this patch.

Is there a chance to get this patch into the kernel? Or
is this solution so special?

Regards
Andy
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