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Date: Fri, 1 Nov 2013 15:08:58 -0700 From: Stephen Boyd <sboyd@...eaurora.org> To: linux-arm-kernel@...ts.infradead.org Cc: Rohit Vaswani <rvaswani@...eaurora.org>, David Brown <davidb@...eaurora.org>, linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org Subject: [PATCH 10/11] ARM: dts: msm: Add nodes necessary for SMP boot From: Rohit Vaswani <rvaswani@...eaurora.org> Add the necessary nodes to support SMP on MSM8960 and MSM8974/APQ8074. While we're here also add in the error interrupts for the krait cache error detection. Signed-off-by: Rohit Vaswani <rvaswani@...eaurora.org> [sboyd: Split into separate patch, add error interrupts] Signed-off-by: Stephen Boyd <sboyd@...eaurora.org> --- arch/arm/boot/dts/qcom-msm8960-cdp.dts | 32 ++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 49 ++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 91efaec..0621037c 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -9,6 +9,32 @@ compatible = "qcom,msm8960-cdp", "qcom,msm8960"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 14 0x304>; + compatible = "qcom,krait"; + enable-method = "qcom,mmio"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; + intc: interrupt-controller@...0000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -53,6 +79,12 @@ #reset-cells = <1>; }; + clock-controller@...8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02008000 0x1000>; + cpu-offset = <0x80000>; + }; + serial@...40000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 152879d..0eac2ea 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -9,6 +9,44 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + enable-method = "qcom,mmio"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -91,6 +129,17 @@ }; }; + regulator@...12000 { + compatible = "qcom,l2-saw2", "qcom,saw2"; + reg = <0xf9012000 0x1000>; + }; + + clock-controller@...08000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9008000 0x1000>; + cpu-offset = <0x80000>; + }; + restart@...ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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