linux-kernel - Re: [PATCH v3 3/5] MCS Lock: Barrier corrections

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Message-ID: <20131107143139.GT18245@linux.vnet.ibm.com>
Date:	Thu, 7 Nov 2013 06:31:39 -0800
From:	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:	Michel Lespinasse <walken@...gle.com>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Waiman Long <waiman.long@...com>,
	Arnd Bergmann <arnd@...db.de>, Rik van Riel <riel@...hat.com>,
	Aswin Chandramouleeswaran <aswin@...com>,
	Raghavendra K T <raghavendra.kt@...ux.vnet.ibm.com>,
	"Figo. zhang" <figo1802@...il.com>, linux-arch@...r.kernel.org,
	Andi Kleen <andi@...stfloor.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	George Spelvin <linux@...izon.com>,
	Tim Chen <tim.c.chen@...ux.intel.com>,
	Ingo Molnar <mingo@...e.hu>,
	Peter Hurley <peter@...leysoftware.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-mm <linux-mm@...ck.org>,
	Andrea Arcangeli <aarcange@...hat.com>,
	Alex Shi <alex.shi@...aro.org>, linux-kernel@...r.kernel.org,
	Scott J Norton <scott.norton@...com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Dave Hansen <dave.hansen@...el.com>,
	Matthew R Wilcox <matthew.r.wilcox@...el.com>,
	Will Deacon <will.deacon@....com>,
	Davidlohr Bueso <davidlohr.bueso@...com>
Subject: Re: [PATCH v3 3/5] MCS Lock: Barrier corrections

On Thu, Nov 07, 2013 at 04:50:23AM -0800, Michel Lespinasse wrote:
> On Thu, Nov 7, 2013 at 4:06 AM, Linus Torvalds
> <torvalds@...ux-foundation.org> wrote:
> >
> > On Nov 7, 2013 6:55 PM, "Michel Lespinasse" <walken@...gle.com> wrote:
> >>
> >> Rather than writing arch-specific locking code, would you agree to
> >> introduce acquire and release memory operations ?
> >
> > Yes, that's probably the right thing to do. What ops do we need? Store with
> > release, cmpxchg and load with acquire? Anything else?
> 
> Depends on what lock types we want to implement on top; for MCS we would need:
> - xchg acquire (common case) and load acquire (for spinning on our
> locker's wait word)
> - cmpxchg release (when there is no next locker) and store release
> (when writing to the next locker's wait word)
> 
> One downside of the proposal is that using a load acquire for spinning
> puts the memory barrier within the spin loop. So this model is very
> intuitive and does not add unnecessary barriers on x86, but it my
> place the barriers in a suboptimal place for architectures that need
> them.

OK, I will bite...  Why is a barrier in the spinloop suboptimal?

Can't say that I have tried measuring it, but the barrier should not
normally result in interconnect traffic.  Given that the barrier is
required anyway, it should not affect lock-acquisition latency.

So what am I missing here?

							Thanx, Paul

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