linux-kernel - Re: [PATCH v3 3/5] MCS Lock: Barrier corrections

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Message-ID: <1383858951.11046.399.camel@schen9-DESK>
Date:	Thu, 07 Nov 2013 13:15:51 -0800
From:	Tim Chen <tim.c.chen@...ux.intel.com>
To:	Michel Lespinasse <walken@...gle.com>
Cc:	Paul McKenney <paulmck@...ux.vnet.ibm.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Waiman Long <waiman.long@...com>,
	Arnd Bergmann <arnd@...db.de>, Rik van Riel <riel@...hat.com>,
	Aswin Chandramouleeswaran <aswin@...com>,
	Raghavendra K T <raghavendra.kt@...ux.vnet.ibm.com>,
	"Figo. zhang" <figo1802@...il.com>, linux-arch@...r.kernel.org,
	Andi Kleen <andi@...stfloor.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	George Spelvin <linux@...izon.com>,
	Ingo Molnar <mingo@...e.hu>,
	Peter Hurley <peter@...leysoftware.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-mm <linux-mm@...ck.org>,
	Andrea Arcangeli <aarcange@...hat.com>,
	Alex Shi <alex.shi@...aro.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Scott J Norton <scott.norton@...com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Dave Hansen <dave.hansen@...el.com>,
	Matthew R Wilcox <matthew.r.wilcox@...el.com>,
	Will Deacon <will.deacon@....com>,
	Davidlohr Bueso <davidlohr.bueso@...com>
Subject: Re: [PATCH v3 3/5] MCS Lock: Barrier corrections

On Thu, 2013-11-07 at 11:59 -0800, Michel Lespinasse wrote:
> On Thu, Nov 7, 2013 at 6:31 AM, Paul E. McKenney
> <paulmck@...ux.vnet.ibm.com> wrote:
> > On Thu, Nov 07, 2013 at 04:50:23AM -0800, Michel Lespinasse wrote:
> >> On Thu, Nov 7, 2013 at 4:06 AM, Linus Torvalds
> >> <torvalds@...ux-foundation.org> wrote:
> >> >
> >> > On Nov 7, 2013 6:55 PM, "Michel Lespinasse" <walken@...gle.com> wrote:
> >> >>
> >> >> Rather than writing arch-specific locking code, would you agree to
> >> >> introduce acquire and release memory operations ?
> >> >
> >> > Yes, that's probably the right thing to do. What ops do we need? Store with
> >> > release, cmpxchg and load with acquire? Anything else?
> >>
> >> Depends on what lock types we want to implement on top; for MCS we would need:
> >> - xchg acquire (common case) and load acquire (for spinning on our
> >> locker's wait word)
> >> - cmpxchg release (when there is no next locker) and store release
> >> (when writing to the next locker's wait word)
> >>
> >> One downside of the proposal is that using a load acquire for spinning
> >> puts the memory barrier within the spin loop. So this model is very
> >> intuitive and does not add unnecessary barriers on x86, but it my
> >> place the barriers in a suboptimal place for architectures that need
> >> them.
> >
> > OK, I will bite...  Why is a barrier in the spinloop suboptimal?
> 
> It's probably not a big deal - all I meant to say is that if you were
> manually placing barriers, you would probably put one after the loop
> instead. I don't deal much with architectures where such barriers are
> needed, so I don't know for sure if the difference means much.

We could do a load acquire at the end of the 
spin loop in the lock function and not in the spin loop itself if cost
of barrier within spin loop is a concern.

Michel, are you planning to do an implementation of
load-acquire/store-release functions of various architectures?

Or is the approach of arch specific memory barrier for MCS 
an acceptable one before load-acquire and store-release
are available?  Are there any technical issues remaining with 
the patchset after including including Waiman's arch specific barrier?

Tim

> 
> > Can't say that I have tried measuring it, but the barrier should not
> > normally result in interconnect traffic.  Given that the barrier is
> > required anyway, it should not affect lock-acquisition latency.
> 
> Agree
> 
> > So what am I missing here?
> 
> I think you read my second email as me trying to shoot down a proposal
> - I wasn't, as I really like the acquire/release model and find it
> easy to program with, which is why I'm proposing it in the first
> place. I just wanted to be upfront about all potential downsides, so
> we can consider them and see if they are significant - I don't think
> they are, but I'm not the best person to judge that as I mostly just
> deal with x86 stuff.
> 


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