linux-kernel - Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver

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Date:	Mon, 11 Nov 2013 16:41:33 +0530
From:	Kishon Vijay Abraham I <kishon@...com>
To:	Jingoo Han <jg1.han@...sung.com>
CC:	"'Vivek Gautam'" <gautamvivek1987@...il.com>,
	"'Kamil Debski'" <k.debski@...sung.com>,
	"'Vivek Gautam'" <gautam.vivek@...sung.com>,
	"'Linux USB Mailing List'" <linux-usb@...r.kernel.org>,
	<linux-samsung-soc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-doc@...r.kernel.org>,
	"'Greg KH'" <gregkh@...uxfoundation.org>,
	"'Kukjin Kim'" <kgene.kim@...sung.com>,
	"'Sylwester Nawrocki'" <s.nawrocki@...sung.com>,
	"'Tomasz Figa'" <t.figa@...sung.com>,
	"'Felipe Balbi'" <balbi@...com>,
	"'Julius Werner'" <jwerner@...omium.org>
Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver

Hi,

On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote:
> On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote:
>> On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han <jg1.han@...sung.com> wrote:
> 
> [.....]
> 
>>> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block.
>>> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block
>>> and 2.0 block, respectively.
>>>
>>> Conclusion:
>>>
>>>    1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device
>>>                        Base address: 0x1213 0000
>>>
>>>    2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device)
>>>                        Base address: 0x1210 0000
>>>                        2.0 block(UTMI+) & 3.0 block(PIPE3)
>>
>> And this is of course the PHY used by DWC3 controller, which works at
>> both High speed as well as Super Speed.
>> Right ?
> 
> Right.
> 
> While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+)
> can be used for High speed.

It should then come under *single IP muliple PHY* category similar to what
Sylwester has done.

Thanks
Kishon
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