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Date: Tue, 12 Nov 2013 10:31:46 -0800 From: "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com> To: "Luck, Tony" <tony.luck@...el.com> Cc: "peterz@...radead.org" <peterz@...radead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org> Subject: Re: Does Itanium permit speculative stores? On Tue, Nov 12, 2013 at 06:00:26PM +0000, Luck, Tony wrote: > > Does Itanium permit speculative stores? For example, on Itanium what are > > the permitted outcomes of the following litmus test, where both x and y > > are initially zero? > > We have a complier visible speculative read via the "ld.s" and "chk" instructions. But > there is no speculative write ("st.s") instruction. I think you are asking "can out of order > writes become visible in this scenario?" > > CPU 0 CPU 1 > > r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y); > if (r1) if (r2) > ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1; > > > In particular, is the outcome (r1 == 1 && r2 == 1) possible on Itanium > > given this litmus test? > > The "ACCESS_ONCE" macro casts to volatile - which will make gcc generate > ordered "ld.acq" and "st.rel" instructions for your code snippets. So I think > you should be fine. Excellent!!! Thank you for the information! If I understand you correctly, this underscores the importance of using ACCESS_ONCE() -- if you omit them in the above scenario, perhaps you can see out-of-order stores becoming visible in this scenario? Also, this resolves our earlier IRC discussion about Itanium's lack of read-read cache coherence. If you use ACCESS_ONCE properly, then on Itanium the reads will become ld.acq instructions, ensuring the expected cache coherence. Very nice! Thanx, Paul -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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