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Message-ID: <1385047851-14407-1-git-send-email-ivan.khoronzhuk@ti.com>
Date: Thu, 21 Nov 2013 17:30:51 +0200
From: Ivan Khoronzhuk <ivan.khoronzhuk@...com>
To: Santosh Shilimkar <santosh.shilimkar@...com>
CC: Mike Turquette <mturquette@...aro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <grygorii.strashko@...com>,
Ivan Khoronzhuk <ivan.khoronzhuk@...com>
Subject: [PATCH] clk: keystone: gate: don't use reserved bits
According to TRM http://www.ti.com/lit/ug/sprugv4b/sprugv4b.pdf
the Power Domain Status Register (PDSTAT) has 0-1 bits for power
domain status, but PDSTAT_STATE_MASK is defined with 0x1F. In that
case we operate with reserved bits. So correct PDSTAT_STATE_MASK
to be 0x03.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@...com>
---
drivers/clk/keystone/gate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/keystone/gate.c b/drivers/clk/keystone/gate.c
index 1f333bc..995ae80 100644
--- a/drivers/clk/keystone/gate.c
+++ b/drivers/clk/keystone/gate.c
@@ -35,7 +35,7 @@
#define MDSTAT_STATE_MASK 0x3f
#define MDSTAT_MCKOUT BIT(12)
-#define PDSTAT_STATE_MASK 0x1f
+#define PDSTAT_STATE_MASK 0x03
#define MDCTL_FORCE BIT(31)
#define MDCTL_LRESET BIT(8)
#define PDCTL_NEXT BIT(0)
--
1.7.9.5
--
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