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Message-ID: <52924132.2080209@c-s.fr>
Date: Sun, 24 Nov 2013 19:10:58 +0100
From: christophe leroy <christophe.leroy@....fr>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Paul Mackerras <paulus@...ba.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...stprotocols.net>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: perf events: how to implement TLB misses as SW event ?
Today in the perfevents subsystem it looks like DTLB/ITLB misses are
implemented as HW counter only.
On some processors, like PowerPC 8xx, there is no counter for that.
However DTLB/ITLB misses are handled as exceptions via software, so we
have an opportunity to implement a SW counter for that.
What's the easiest/best way to implement it ?
Christophe
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