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Message-Id: <201312052140.42269.arnd@arndb.de>
Date: Thu, 5 Dec 2013 21:40:42 +0100
From: Arnd Bergmann <arnd@...db.de>
To: Hanjun Guo <hanjun.guo@...aro.org>
Cc: linux-arm-kernel@...ts.infradead.org,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
"Russell King - ARM Linux" <linux@....linux.org.uk>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Mark Rutland <mark.rutland@....com>,
Matthew Garrett <mjg59@...f.ucam.org>,
linaro-kernel@...ts.linaro.org,
Graeme Gregory <graeme.gregory@...aro.org>,
Al Stone <al.stone@...aro.org>, patches@...aro.org,
Linus Walleij <linus.walleij@...aro.org>,
Olof Johansson <olof@...om.net>, linux-kernel@...r.kernel.org,
Rob Herring <rob.herring@...xeda.com>,
linaro-acpi@...ts.linaro.org, linux-acpi@...r.kernel.org,
Jon Masters <jonathan@...masters.org>,
Grant Likely <grant.likely@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [RFC part1 PATCH 5/7] ARM64 / ACPI: Introduce arm_core.c and its related head file
On Thursday 05 December 2013, Hanjun Guo wrote:
> On 2013年12月05日 11:38, Arnd Bergmann wrote:
> > On Tuesday 03 December 2013, Hanjun Guo wrote:
> >> +static unsigned int gsi_to_irq(unsigned int gsi)
> >> +{
> >> + int irq = irq_create_mapping(NULL, gsi);
> >> +
> >> + return irq;
> >> +}
> > I think this could use a comment regarding your plans for IRQ domains.
> >
> > Do you expect that all ACPI systems would have only a single GIC IRQ
> > controller and a single domain, or do you plan to add irqdomain code
> > later?
>
> we added irqdomain code in the part2 patch set, is that the code ok
> with you?
I don't see where it gets added. Do you mean "[RFC part2 PATCH 8/9] ACPI /
ARM64: Update acpi_register_gsi to register with the core IRQ subsystem"?
That still just uses a single domain.
When we talked about ACPI support at Linaro connect, someone mentioned
that the ACPI spec does have the concept of IRQ domains, but it seems
they are not implemented by Linux.
How do you get a mapping for an IRQ on a secondary irqchip such as
a GPIO extender?
Arnd
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