linux-kernel - [tip:x86/cpufeature] x86, cpufeature: Define the Intel MPX feature flag

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Message-ID: <tip-191f57c137bcce0e3e9313acb77b2f114d15afbb@git.kernel.org>
Date:	Fri, 6 Dec 2013 10:25:11 -0800
From:	tip-bot for Qiaowei Ren <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, qiaowei.ren@...el.com, hpa@...or.com,
	mingo@...nel.org, jinsong.liu@...el.com, xudong.hao@...el.com,
	tglx@...utronix.de, hpa@...ux.intel.com
Subject: [tip:x86/cpufeature] x86, cpufeature:
  Define the Intel MPX feature flag

Commit-ID:  191f57c137bcce0e3e9313acb77b2f114d15afbb
Gitweb:     http://git.kernel.org/tip/191f57c137bcce0e3e9313acb77b2f114d15afbb
Author:     Qiaowei Ren <qiaowei.ren@...el.com>
AuthorDate: Sat, 7 Dec 2013 08:20:57 +0800
Committer:  H. Peter Anvin <hpa@...ux.intel.com>
CommitDate: Fri, 6 Dec 2013 10:21:44 -0800

x86, cpufeature: Define the Intel MPX feature flag

Define the Intel MPX (Memory Protection Extensions) CPU feature flag
in the cpufeature list.

Signed-off-by: Qiaowei Ren <qiaowei.ren@...el.com>
Link: http://lkml.kernel.org/r/1386375658-2191-2-git-send-email-qiaowei.ren@intel.com
Signed-off-by: Xudong Hao <xudong.hao@...el.com>
Signed-off-by: Liu Jinsong <jinsong.liu@...el.com>
Signed-off-by: H. Peter Anvin <hpa@...ux.intel.com>
---
 arch/x86/include/asm/cpufeature.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 89270b4..e099f95 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -216,6 +216,7 @@
 #define X86_FEATURE_ERMS	(9*32+ 9) /* Enhanced REP MOVSB/STOSB */
 #define X86_FEATURE_INVPCID	(9*32+10) /* Invalidate Processor Context ID */
 #define X86_FEATURE_RTM		(9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_MPX		(9*32+14) /* Memory Protection Extension */
 #define X86_FEATURE_RDSEED	(9*32+18) /* The RDSEED instruction */
 #define X86_FEATURE_ADX		(9*32+19) /* The ADCX and ADOX instructions */
 #define X86_FEATURE_SMAP	(9*32+20) /* Supervisor Mode Access Prevention */
--
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