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Message-ID: <52A73301.3030905@linaro.org>
Date: Tue, 10 Dec 2013 23:28:01 +0800
From: Alex Shi <alex.shi@...aro.org>
To: Arjan van de Ven <arjan@...ux.intel.com>,
Preeti U Murthy <preeti@...ux.vnet.ibm.com>
CC: Daniel Lezcano <daniel.lezcano@...aro.org>,
Frederic Weisbecker <fweisbec@...il.com>,
LAK <linux-arm-kernel@...ts.infradead.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"len.brown@...el.com" <len.brown@...el.com>,
rafael.j.wysocki@...el.com
Subject: Re: questions of cpuidle
On 12/10/2013 10:53 PM, Arjan van de Ven wrote:
> On 12/9/2013 10:08 PM, Alex Shi wrote:
>> And for monitor/mwait idle method, seems deep c-state cpu need to keep a
>> eye on memory bus. So seems the memory controller in cpu package is
>> impossible to get into sleep, right?
> not the memory bus
> the cache coherency logic ;-)
>
Thanks a lot, Arjan!
But in Intel c7 state, l3 cache also flushed. Are there some other unit
monitor this?
--
Thanks
Alex
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