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Message-Id: <1386702658-21430-2-git-send-email-will.deacon@arm.com>
Date: Tue, 10 Dec 2013 19:10:58 +0000
From: Will Deacon <will.deacon@....com>
To: linux-kernel@...r.kernel.org
Cc: viro@...iv.linux.org.uk, torvalds@...ux-foundation.org,
Will Deacon <will.deacon@....com>
Subject: [PATCH 2/2] word-at-a-time: provide generic big-endian zero_bytemask implementation
Whilst architectures may be able to do better than this (which they can,
by simply defining their own macro), this is a generic stab at a
zero_bytemask implementation for the asm-generic, big-endian
word-at-a-time implementation.
On arm64, a clz instruction is used to implement the fls efficiently.
Signed-off-by: Will Deacon <will.deacon@....com>
---
I'm happy to move this into the arch/ backends, but there's a strong
linkage between this and the generic word-at-a-time algorithm that could
easily break if they don't live together.
include/asm-generic/word-at-a-time.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/asm-generic/word-at-a-time.h b/include/asm-generic/word-at-a-time.h
index 3f21f1b72e45..d3909effd725 100644
--- a/include/asm-generic/word-at-a-time.h
+++ b/include/asm-generic/word-at-a-time.h
@@ -49,4 +49,12 @@ static inline bool has_zero(unsigned long val, unsigned long *data, const struct
return (val + c->high_bits) & ~rhs;
}
+#ifndef zero_bytemask
+#ifdef CONFIG_64BIT
+#define zero_bytemask(mask) (~0ul << fls64(mask))
+#else
+#define zero_bytemask(mask) (~0ul << fls(mask))
+#endif /* CONFIG_64BIT */
+#endif /* zero_bytemask */
+
#endif /* _ASM_WORD_AT_A_TIME_H */
--
1.8.2.2
--
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