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Message-ID: <DE8DF0795D48FD4CA783C40EC82923350141B4A7@SHSMSX101.ccr.corp.intel.com>
Date: Wed, 11 Dec 2013 08:31:35 +0000
From: "Liu, Jinsong" <jinsong.liu@...el.com>
To: "pbonzini@...hat.com" <pbonzini@...hat.com>,
"gleb@...hat.com" <gleb@...hat.com>,
"hpa@...or.com" <hpa@...or.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"qemu-devel@...gnu.org" <qemu-devel@...gnu.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 0/4] X86/KVM: enable Intel MPX for KVM
Paolo, comments for version 2?
Thanks,
Jinsong
Liu, Jinsong wrote:
> These patches are version 2 to enalbe Intel MPX for KVM.
>
> Version 1:
> * Add some Intel MPX definiation
> * Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features
> enable/disable
> * vmx and msr handle for MPX support at KVM
> * enalbe MPX feature for guest
>
> Version 2:
> * remove generic MPX definiation, kernel side has add the
> definiation
> * add MSR_IA32_BNDCFGS to msrs_to_save
>
> Thanks,
> Jinsong
>
> Liu Jinsong (4):
> KVM/X86: Fix xsave cpuid exposing bug
> KVM/X86: Intel MPX vmx and msr handle
> KVM/X86: add MSR_IA32_BNDCFGS to msrs_to_save
> KVM/X86: Enable Intel MPX for guest.
>
> arch/x86/include/asm/vmx.h | 4 ++++
> arch/x86/include/asm/xsave.h | 2 ++
> arch/x86/include/uapi/asm/msr-index.h | 1 +
> arch/x86/kvm/cpuid.c | 8 ++++----
> arch/x86/kvm/vmx.c | 18 ++++++++++++++++--
> arch/x86/kvm/x86.c | 12 +++++++++---
> arch/x86/kvm/x86.h | 3 ++-
> 7 files changed, 38 insertions(+), 10 deletions(-)
--
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