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Message-ID: <CAAYSxhr10XqQdQrvGf3Ez6e4LSbvmc0J-=yRgUePVEcd93e5wQ@mail.gmail.com>
Date:	Wed, 11 Dec 2013 13:00:33 -0800
From:	Tim Kryger <tim.kryger@...aro.org>
To:	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc:	James Hogan <james@...anarts.com>, linux-serial@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Lior Amsalem <alior@...vell.com>,
	Jason Cooper <jason@...edaemon.net>,
	James Hogan <james.hogan@...tec.com>,
	Jiri Slaby <jslaby@...e.cz>,
	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
	Matt Porter <matt.porter@...aro.org>,
	Markus Mayer <markus.mayer@...aro.org>
Subject: Re: [PATCH] serial: 8250_dw: Fix LCR workaround regression

On Wed, Dec 11, 2013 at 6:00 AM, Heikki Krogerus
<heikki.krogerus@...ux.intel.com> wrote:
> Hi,
>
> On Tue, Dec 10, 2013 at 10:28:04PM +0000, James Hogan wrote:
>> From: James Hogan <james.hogan@...tec.com>
>>
>> Commit c49436b657d0 (serial: 8250_dw: Improve unwritable LCR workaround)
>> caused a regression. It added a check that the LCR was written properly
>> to detect and workaround the busy quirk, but the behaviour of bit 5
>> (UART_LCR_SPAR) differs between IP versions 3.00a and 3.14c per the
>> docs. On older versions this caused the check to fail and it would
>> repeatedly force idle and rewrite the LCR register, causing delays and
>> preventing any input from serial being received.
>>
>> This is fixed by masking out UART_LCR_SPAR before making the comparison.
>>
>> Signed-off-by: James Hogan <james.hogan@...tec.com>
>> Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
>> Cc: Jiri Slaby <jslaby@...e.cz>
>> Cc: Tim Kryger <tim.kryger@...aro.org>
>> Cc: Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>
>> Cc: Matt Porter <matt.porter@...aro.org>
>> Cc: Markus Mayer <markus.mayer@...aro.org>
>> Cc: Heikki Krogerus <heikki.krogerus@...ux.intel.com>
>> Tested-by: Tim Kryger <tim.kryger@...aro.org>
>> Tested-by: Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>
>
> I tested this with HW without the busy functionality
> (UART_16550_COMPATIBLE == yes). No problems here. FWIW:
>
> Tested-by: Heikki Krogerus <heikki.krogerus@...ux.intel.com>

Greg, can you consider taking this patch as a regression fix for 3.13?

Just in case you want a little more background beyond what is in the
commit message...

Statically declared DW UARTs will execute autoconfig_16550a during
probe which attempts to set the SPAR bit of LCR.  Some old versions of
the DW IP don't implement the stick parity feature and for these
versions the SPAR bit always reads back as zero. Since these writes
aren't fully accepted by the hardware, they trigger the workaround
which interprets the partially rejected write to mean the UART was
busy.  A number of attempts are made to idle the UART and re-write the
LCR but eventually the workaround gives up and prints a warning.  DT
declared DW UARTs don't run autoconfig and don't see this issue as far
as I know.

Thanks,
Tim Kryger
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