linux-kernel - Re: [PATCHv7 1/4] pwm: Add Freescale FTM PWM driver support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20131217124505.GB17210@ulmo.nvidia.com>
Date:	Tue, 17 Dec 2013 13:45:06 +0100
From:	Thierry Reding <thierry.reding@...il.com>
To:	Tomasz Figa <tomasz.figa@...il.com>
Cc:	Russell King - ARM Linux <linux@....linux.org.uk>,
	Xiubo Li <Li.Xiubo@...escale.com>, mark.rutland@....com,
	s.hauer@...gutronix.de, galak@...eaurora.org,
	swarren@...dotorg.org, t.figa@...sung.com, grant.likely@...aro.org,
	matt.porter@...aro.org, rob@...dley.net, ian.campbell@...rix.com,
	pawel.moll@....com, rob.herring@...xeda.com,
	linux-arm-kernel@...ts.infradead.org, linux-pwm@...r.kernel.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	linux-doc@...r.kernel.org, Alison Wang <b18965@...escale.com>,
	Jingchang Lu <b35083@...escale.com>
Subject: Re: [PATCHv7 1/4] pwm: Add Freescale FTM PWM driver support

On Tue, Dec 17, 2013 at 01:00:10PM +0100, Tomasz Figa wrote:
> On Tuesday 17 of December 2013 11:51:36 Russell King - ARM Linux wrote:
> > On Tue, Dec 17, 2013 at 12:10:22PM +0100, Thierry Reding wrote:
> > > On Fri, Dec 13, 2013 at 04:57:04PM +0800, Xiubo Li wrote:
> > > > +static inline u32 fsl_pwm_readl(struct fsl_pwm_chip *fpc,
> > > > +		const void __iomem *addr)
> > > > +{
> > > > +	u32 val;
> > > > +
> > > > +	val = __raw_readl(addr);
> > > > +
> > > > +	if (likely(fpc->big_endian))
> > > 
> > > The likely() probably isn't very useful in this case. But if you want to
> > > keep it, it should at least be reversed, since little-endian is actually
> > > the default (you have to specify the big-endian property to activate the
> > > big endian mode).
> > > 
> > > > +		val = be32_to_cpu(val);
> > > > +	else
> > > > +		val = le32_to_cpu(val);
> > 
> > This will also cause sparse errors, because when sparse is enabled, these
> > expect __le32 or __be32 arguments, not u32.
> 
> My question is why can't you just create two sets of accessors, one big
> endian and one little endian, add two function pointers to your
> fsl_pwm_chip struct and let the driver set the to correct accessors in
> probe?

I guess that would be one possibility.

> This would eliminate the problem with types Russell mentioned and IMHO
> make the code cleaner.

I fail to see how that would eliminate the problem with the types. That
said I don't actually see sparse complaining about any type mismatches.
That's probably because the various macros implicitly cast to u32.

> > > > +	rmb();
> > > 
> > > I'd prefer the rmb() to follow the __raw_readl() immediately to make the
> > > relationship more explicit.
> > 
> > A better question to ask is: why is this barrier here?  What memory
> > ordering operations is it trying to serialise?
> 
> I'd also add a question why __raw accessors are used here.

Because both readl() and writel() explicitly perform little endian
accesses.

Thierry

Content of type "application/pgp-signature" skipped