linux-kernel - Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow tracing units

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Message-ID: <20131218150900.GU21999@twins.programming.kicks-ass.net>
Date:	Wed, 18 Dec 2013 16:09:00 +0100
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	David Ahern <dsahern@...il.com>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Jiri Olsa <jolsa@...hat.com>, Mike Galbraith <efault@....de>,
	Namhyung Kim <namhyung@...il.com>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow
 tracing units

On Wed, Dec 18, 2013 at 04:22:36PM +0200, Alexander Shishkin wrote:
> > Still confused, if you cannot copy it into one buffer, then why can you
> > copy it into a second buffer?
> 
> It's not copied, hardware writes directly into that second buffer.

Where's the PT documentation? I can't find it in the SDM and your ISA
extensions link is a generic Intel website which is friggin useless
(like all corporate websites strive to be).

Your actual PT patch doesn't describe how the things works either, and
while I could go read the code, I'm too lazy.

The thing is; why can't you zero-copy whatever buffer the hardware
writes into, into the normal buffer?

Machinery like that would also be useful to zero-copy bits out of the
buffer right into the page-cache.

> I've done the same with BTS now (as Ingo suggested) and it also benefits
> from this approach.

The problem with DS is that it needs physically contiguous pages is it
not? So you cannot really allocate a large buffer, and you end up
needing to copy or swizzle stuff.
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