linux-kernel - Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow tracing units

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Date:	Thu, 19 Dec 2013 12:57:59 +0100
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	David Ahern <dsahern@...il.com>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Jiri Olsa <jolsa@...hat.com>, Mike Galbraith <efault@....de>,
	Namhyung Kim <namhyung@...il.com>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow
 tracing units

On Thu, Dec 19, 2013 at 12:28:12PM +0100, Peter Zijlstra wrote:
> This document you referred me to looks to specify something with a
> proper s/g implementation; called ToPA. There doesn't appear to be a
> limit to the linked entries and you can specify a size per entry, and I
> don't see anywhere why 4k would be bad.
> 
> That said, I'm still reading..

Found it:

"Single Output Region ToPA Implementation

The first processor generation to implement Intel PT supports only ToPA
configurations with a single ToPA entry followed by an END entry that
points back to the first entry (creating one circular output buffer).
Such processors enumerate CPUID.(EAX=14H,ECX=0):EBX[bit 1] as 0."

So basically you guys buggered the hardware.

More specifically, what actual hardware is this? Is this first
generation HSW or so?

Please enumerate the actual hardware that supports this PT stuff and
which hardware has it fixed.
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