linux-kernel - Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow tracing units

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Message-ID: <20131219125759.GU3694@twins.programming.kicks-ass.net>
Date:	Thu, 19 Dec 2013 13:57:59 +0100
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	David Ahern <dsahern@...il.com>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Jiri Olsa <jolsa@...hat.com>, Mike Galbraith <efault@....de>,
	Namhyung Kim <namhyung@...il.com>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH v0 04/71] itrace: Infrastructure for instruction flow
 tracing units

On Thu, Dec 19, 2013 at 12:57:59PM +0100, Peter Zijlstra wrote:
> On Thu, Dec 19, 2013 at 12:28:12PM +0100, Peter Zijlstra wrote:
> > This document you referred me to looks to specify something with a
> > proper s/g implementation; called ToPA. There doesn't appear to be a
> > limit to the linked entries and you can specify a size per entry, and I
> > don't see anywhere why 4k would be bad.
> > 
> > That said, I'm still reading..
> 
> Found it:
> 
> "Single Output Region ToPA Implementation
> 
> The first processor generation to implement Intel PT supports only ToPA
> configurations with a single ToPA entry followed by an END entry that
> points back to the first entry (creating one circular output buffer).
> Such processors enumerate CPUID.(EAX=14H,ECX=0):EBX[bit 1] as 0."
> 
> So basically you guys buggered the hardware.
> 

"ToPA PMI and Single Output Region ToPA Implementation

A processor that supports only a single ToPA output region
implementation (such that only one output region is supported; see
above) will attempt to signal a ToPA PMI interrupt before the output
wraps and overwrites the top of the buffer. To support this
functionality, the PMI handler should disable packet generation as soon
as possible.  Due to PMI skid, it is possible, in rare cases, that the
wrap will have occurred before the PMI is delivered. Software can avoid
this by setting the STOP bit in the ToPA entry (see Table 11-3); this
will disable tracing once the region is filled, and no wrap will occur.
This approach has the downside of disabling packet generation so that
some of the instructions that led up to the PMI will not be traced. If
the PMI skid is significant enough to cause the region to fill and
tracing to be disabled, the PMI handler will need to clear the
IA32_RTIT_STATUS.Stopped indication before tracing can resume."

So you're basically forced to stop the tracing on PMI anyhow; so your
continuous tracing argument goes out the window.

Also, what a complete clusterfuck. I think we're far better of
pretending PT doesn't exist until its fixed.
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