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Message-Id: <1388105067-24438-5-git-send-email-abrestic@chromium.org>
Date: Thu, 26 Dec 2013 16:44:24 -0800
From: Andrew Bresticker <abrestic@...omium.org>
To: Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>
Cc: Thierry Reding <thierry.reding@...il.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Mark Zhang <markz@...dia.com>,
Andrew Bresticker <abrestic@...omium.org>
Subject: [PATCH 4/7] clk: tegra: fix host1x clock on Tegra124
From: Mark Zhang <markz@...dia.com>
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.
Signed-off-by: Mark Zhang <markz@...dia.com>
Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
---
drivers/clk/tegra/clk-tegra124.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 0fc9126..743ccb4 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -775,7 +775,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true },
[tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
[tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
- [tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
+ [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
[tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
[tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
[tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
--
1.8.5.1
--
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