lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <cover.1389018985.git.michal.simek@xilinx.com>
Date:	Mon,  6 Jan 2014 15:36:36 +0100
From:	Michal Simek <michal.simek@...inx.com>
To:	linux-arm-kernel@...ts.infradead.org,
	Arnd Bergmann <arnd@...db.de>,
	Soren Brinkmann <soren.brinkmann@...inx.com>,
	Steffen Trumtrar <s.trumtrar@...gutronix.de>
Cc:	Mike Turquette <mturquette@...aro.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>, monstr@...str.eu,
	devicetree@...r.kernel.org, Stephen Boyd <sboyd@...eaurora.org>,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
	Stephen Warren <swarren@...dotorg.org>,
	Peter Crosthwaite <peter.crosthwaite@...inx.com>,
	Russell King <linux@....linux.org.uk>,
	Rob Herring <rob.herring@...xeda.com>,
	Pawel Moll <pawel.moll@....com>,
	Rob Herring <robherring2@...il.com>,
	Mark Rutland <mark.rutland@....com>,
	Josh Cartwright <josh.cartwright@...com>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Rob Landley <rob@...dley.net>
Subject: [PATCH 0/7] Xilinx Zynq SLCR changes

Hi,

I have rebased and added together patches I have got from Steffen some time ago.
Steffen: I kept there your SoB. Please let me know if there is any problem
with it.

The point of this series is to use slcr as system controller
to be able to create other drivers like pinmux, etc.

These patches are based on zynq/cleanup and zynq/dt branches merged
together. (They are available in arm-soc git tree).
Let me know if you want to add the branch somewhere.

Arnd: We talked at KS about syscon early initialization which
will be really helpful for this case. Has someone done any work
around it?

Thanks,
Michal


Michal Simek (4):
  ARM: zynq: Split slcr in two parts
  ARM: zynq: Map I/O memory on clkc init
  ARM: zynq: Add and use zynq_slcr_read/write() helper functions
  ARM: zynq: Introduce zynq_slcr_unlock()

Steffen Trumtrar (3):
  ARM: zynq: Move clock_init from slcr to common
  ARM: zynq: Hang iomapped slcr address on device_node
  ARM: zynq: Make zynq_slcr_base static

 .../devicetree/bindings/clock/zynq-7000.txt        |  4 +-
 arch/arm/boot/dts/zynq-7000.dtsi                   | 42 +++++-----
 arch/arm/mach-zynq/Kconfig                         |  1 +
 arch/arm/mach-zynq/common.c                        |  6 +-
 arch/arm/mach-zynq/common.h                        |  2 +-
 arch/arm/mach-zynq/slcr.c                          | 98 +++++++++++++++++++---
 drivers/clk/zynq/clkc.c                            | 89 ++++++++++++++------
 include/linux/clk/zynq.h                           |  2 +-
 8 files changed, 179 insertions(+), 65 deletions(-)

--
1.8.2.3


Content of type "application/pgp-signature" skipped

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ