linux-kernel - Re: [PATCH] arm: mm: add memory type for inner-writeback

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Message-ID: <CAMbhsRR-ZuNjauOje9XoKTBVJ=2upRt6_+xqC3XjTCSCZtDJRQ@mail.gmail.com>
Date:	Tue, 7 Jan 2014 13:37:59 -0800
From:	Colin Cross <ccross@...roid.com>
To:	Catalin Marinas <catalin.marinas@....com>
Cc:	Mark Zhang <markz@...dia.com>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"steve.capper@...aro.org" <steve.capper@...aro.org>,
	"nico@...aro.org" <nico@...aro.org>,
	Will Deacon <Will.Deacon@....com>,
	"lauraa@...eaurora.org" <lauraa@...eaurora.org>,
	"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
	"christoffer.dall@...aro.org" <christoffer.dall@...aro.org>,
	"viro@...iv.linux.org.uk" <viro@...iv.linux.org.uk>,
	"gregory.clement@...e-electrons.com" 
	<gregory.clement@...e-electrons.com>,
	"ben-linux@...ff.org" <ben-linux@...ff.org>,
	"paul.gortmaker@...driver.com" <paul.gortmaker@...driver.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Gary King <gking@...dia.com>
Subject: Re: [PATCH] arm: mm: add memory type for inner-writeback

On Tue, Jan 7, 2014 at 7:09 AM, Catalin Marinas <catalin.marinas@....com> wrote:
> On Fri, Dec 27, 2013 at 04:58:48AM +0000, Mark Zhang wrote:
>> From: Colin Cross <ccross@...roid.com>
>>
>> For streaming-style operations (e.g., software rendering of graphics
>> surfaces shared with non-coherent DMA devices), the cost of performing
>> L2 cache maintenance can exceed the benefit of having the larger cache
>> (this is particularly true for OUTER_CACHE configurations like the ARM
>> PL2x0).
>>
>> This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
>> in the tex remapping tables as an inner-writeback-write-allocate, outer
>> non-cacheable memory type, so that this mapping will be available to
>> clients which will benefit from the reduced L2 maintenance.
>>
>> Signed-off-by: Gary King <gking@...dia.com>
>
> Is Colin signing off this patch as well?
>
>> --- a/arch/arm/mm/proc-v7-2level.S
>> +++ b/arch/arm/mm/proc-v7-2level.S
>> @@ -144,8 +144,8 @@ ENDPROC(cpu_v7_set_pte_ext)
>>        *   NS1 = PRRR[19] = 1         - normal shareable property
>>        *   NOS = PRRR[24+n] = 1       - not outer shareable
>>        */
>> -.equ PRRR,   0xff0a81a8
>> -.equ NMRR,   0x40e040e0
>> +.equ PRRR,   0xff0a89a8
>> +.equ NMRR,   0x40e044e0
>
> It should be done for the *-3level files.
>
> --
> Catalin

I shouldn't have authorship on that patch at all.  The original is at
https://android.googlesource.com/kernel/tegra/+/fb382752691d74a849996daf77be961ca2cdae97
and I must have screwed up the authorship when fixing conflicts when
cherry-picking it to the android-tegra-moto-2.6.39 branch.  Please
change the author back to "Gary King <gking@...dia.com>".
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