linux-kernel - Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <52CEF9E7.4070706@arm.com>
Date:	Thu, 09 Jan 2014 19:35:03 +0000
From:	Sudeep Holla <Sudeep.Holla@....com>
To:	Russell King - ARM Linux <linux@....linux.org.uk>
CC:	Sudeep.Holla@....com, "x86@...nel.org" <x86@...nel.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Rob Herring <robh@...nel.org>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Ashok Raj <ashok.raj@...el.com>
Subject: Re: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information

On 08/01/14 20:57, Russell King - ARM Linux wrote:
> On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:
>> +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */
>> +
>> +#define MAX_CACHE_LEVEL		1	/* Only 1 level supported */
>> +#define CTR_CTYPE_SHIFT		24
>> +#define CTR_CTYPE_MASK		(1 << CTR_CTYPE_SHIFT)
>> +
>> +static inline unsigned int get_ctr(void)
>> +{
>> +	unsigned int ctr;
>> +	asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
>> +	return ctr;
>> +}
>> +
>> +static enum cache_type get_cache_type(int level)
>> +{
>> +	if (level > MAX_CACHE_LEVEL)
>> +		return CACHE_TYPE_NOCACHE;
>> +	return get_ctr() & CTR_CTYPE_MASK ?
>> +		CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;
> 
> So, what do we do for CPUs that don't implement the CTR?  Just return
> random rubbish based on decoding the CPU Identity register as if it
> were the cache type register?
> 

I assume you referring to some particular CPUs which don't implement this.
I could not find it as optional or IMPLEMENTATION defined in ARM ARM.
I might be missing to find it or there may be exceptions.
Can you please provide more information on that ?

Regards,
Sudeep

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/