linux-kernel - Re: [patch/rfc] perf on raspberry-pi without overflow interrupt

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Message-ID: <alpine.DEB.2.10.1401132344570.20155@vincent-weaver-1.um.maine.edu>
Date:	Mon, 13 Jan 2014 23:55:17 -0500 (EST)
From:	Vince Weaver <vincent.weaver@...ne.edu>
To:	Peter Zijlstra <peterz@...radead.org>
cc:	Will Deacon <will.deacon@....com>,
	Chad Paradis <chad.paradis@...t.maine.edu>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Stephane Eranian <eranian@...il.com>
Subject: Re: [patch/rfc] perf on raspberry-pi without overflow interrupt

On Fri, 10 Jan 2014, Peter Zijlstra wrote:

> On Thu, Jan 09, 2014 at 11:08:47PM -0500, Vince Weaver wrote:
> > On Thu, 9 Jan 2014, Will Deacon wrote:
> > 
> > > I'd rather see it in the generic code if at all possible. Maybe we could add
> > > a flags field to perf_pmu_register?
> > 
> > I can look into adding the check in generic code.
> 
> Adding something like this to the generic code would mean adding a
> struct pmu capabilities field and visiting all existing PMU
> implementations to properly fill this out.

I don't see an existing pmu capabilities struct... or do you mean
coming up with one?

Would it only hold an "overflow_interrupt_available" flag, or are
there other generic capabilities it would be handy to know about?

> There's a number of hardware PMU implementations that do not have an
> interrupt and would need to set this flag.

Well that can be added gradually, right?  Things wouldn't get any worse if 
we add a generic check without auditing all code, things will just behave 
the same as before for those architectures.

There is some subtlety here though.  On ARM (or at least rasp-pi) the 
overflow hardware is there, just no interrupt is hooked up.  So things 
like counter overflow are handled as long as overflows aren't faster than 
context switch time.  It's just sampled events aren't possible.

On architectures without overflow support at all (I've had such hardware; 
some SPARC machines, the Playstation 3 hypervisor) then counter overflow 
isn't possible without a periodic timer (sort of like what is done with 
Intel uncore).  Is that something that should be in generic code too?

Vince
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