linux-kernel - Re: [PATCH 5/8 v4] clk: samsung: exynos5250/5420: Add gate clock for SSS module

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Date:	Fri, 24 Jan 2014 16:26:38 +0100
From:	Tomasz Figa <t.figa@...sung.com>
To:	Naveen Krishna Chatradhi <ch.naveen@...sung.com>,
	linux-crypto@...r.kernel.org, linux-samsung-soc@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, vzapolskiy@...il.com,
	herbert@...dor.apana.org.au, naveenkrishna.ch@...il.com,
	cpgs@...sung.com, tomasz.figa@...il.com,
	Kukjin Kim <kgene.kim@...sung.com>
Subject: Re: [PATCH 5/8 v4] clk: samsung: exynos5250/5420: Add gate clock for
 SSS module

Hi Naveen,

Exynos5250 specific part looks good, but I have a little doubt in case 
of Exynos5420.

On 15.01.2014 10:16, Naveen Krishna Chatradhi wrote:
> This patch adds gating clock for SSS(Security SubSystem)
> module on Exynos5250/5420.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@...sung.com>
> TO: <linux-samsung-soc@...r.kernel.org>
> TO: Tomasz Figa <t.figa@...sung.com>
> CC: Kukjin Kim <kgene.kim@...sung.com>
> CC: <linux-crypto@...r.kernel.org>
> ---
> Changes since v3:
> 1. Rebased on to https://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk.git
> 2. Added new ID for SSS clock on Exynos5250, with Documentation and
> 3. Added gate clocks definitions for SSS on Exynos5420 and Exynos5250
[snip]
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -26,6 +26,7 @@
>   #define DIV_CPU1		0x504
>   #define GATE_BUS_CPU		0x700
>   #define GATE_SCLK_CPU		0x800
> +#define GATE_BUS_G2D		0x8700
>   #define CPLL_LOCK		0x10020
>   #define DPLL_LOCK		0x10030
>   #define EPLL_LOCK		0x10040
> @@ -702,6 +703,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   		0),
>   	GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
>   		0),
> +
> +	/* SSS */
> +	GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_BUS_G2D, 2, 0, 0),

Isn't there a combined gate for all SSS clocks in one of GATE_IP_* 
registers?

Best regards,
Tomasz
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