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Message-ID: <1391008584.11756.59.camel@joe-AO722>
Date: Wed, 29 Jan 2014 07:16:24 -0800
From: Joe Perches <joe@...ches.com>
To: Jean-Francois Moine <moinejf@...e.fr>
Cc: dri-devel@...ts.freedesktop.org, Dave Airlie <airlied@...il.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Rob Clark <robdclark@...il.com>,
Russell King - ARM Linux <linux@....linux.org.uk>
Subject: Re: [PATCH v5 17/23] drm/i2c: tda998x: set the PLL division factor
in range 0..3
On Sat, 2014-01-25 at 18:14 +0100, Jean-Francois Moine wrote:
> The predivider division factor of the register PLL_SERIAL_2 is in the
> range 0..3, the value 0 being used for a division by 1.
trivia:
> diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
[]
> @@ -886,6 +886,11 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder,
> }
>
> div = 148500 / mode->clock;
> + if (div != 0) {
> + div--;
> + if (div > 3)
> + div = 3;
> + }
perhaps
clamp(div, 1, 4)
div--;
--
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