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Message-ID: <20140130180533.GH5002@laptop.programming.kicks-ass.net>
Date: Thu, 30 Jan 2014 19:05:33 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Will Deacon <will.deacon@....com>
Cc: Waiman Long <Waiman.Long@...com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, Arnd Bergmann <arnd@...db.de>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Steven Rostedt <rostedt@...dmis.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Michel Lespinasse <walken@...gle.com>,
Andi Kleen <andi@...stfloor.org>,
Rik van Riel <riel@...hat.com>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Raghavendra K T <raghavendra.kt@...ux.vnet.ibm.com>,
George Spelvin <linux@...izon.com>,
Tim Chen <tim.c.chen@...ux.intel.com>,
"Aswin Chandramouleeswaran\"" <aswin@...com>,
Scott J Norton <scott.norton@...com>,
"will@...ldeacon.co.uk" <will@...ldeacon.co.uk>
Subject: Re: [PATCH v11 0/4] Introducing a queue read/write lock
implementation
On Thu, Jan 30, 2014 at 05:52:12PM +0000, Will Deacon wrote:
> It would be nice if these were default implementations of the unlock, then
> architectures just implement atomic_sub_release how they like.
Yes, I suppose that makes sense. Last time I proposed the primitive
nobody yelled at me, so I suppose that means people agree :-)
> One thing worth mentioning: I have a fairly invasive set of changes pending
> for arch/arm64/include/asm/atomic.h, so if you do decide to go with this,
> I'm more than happy to take the sub_release part via the arm64 tree. I guess
> it depends on when this is likely to get merged.
I suppose it depends on when I get enough courage to do: vim
arch/*/include/asm/atomic*.h :-)
There's a few other cleanups I want to do, like today I found
atomic_{set,clear}_mask() instead of the more natural atomic_{or,and}()
functions.
I also think we can get rid of the {inc,dec} variants of
smp_mb__{before,after}_atomic() since these barriers should be the same
for _all_ atomic ops that do not already imply full mb semantics, and
they're certainly the same for all current inc/dec.
If tomorrow is another slow day and I get through enough of the review
backlog I might just give it a go.
Anyway, I'll base them on your arm64 changes, I know where to find
those.
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