Message-ID: <20140203233137.GH2519@obsidianresearch.com>
Date:	Mon, 3 Feb 2014 16:31:37 -0700
From:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
To:	Rob Herring <robherring2@...il.com>
Cc:	Arnd Bergmann <arnd@...db.de>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linaro-kernel@...ts.linaro.org" <linaro-kernel@...ts.linaro.org>,
	linux-pci <linux-pci@...r.kernel.org>,
	Liviu Dudau <Liviu.Dudau@....com>,
	LKML <linux-kernel@...r.kernel.org>,
	Catalin Marinas <Catalin.Marinas@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	LAKML <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: Add architecture support for PCI

On Mon, Feb 03, 2014 at 05:07:48PM -0600, Rob Herring wrote:

> > An interesting question however is what the transition plan is to
> > have the code shared between arm32 and arm64: We will certainly need
> > to share at least the dw-pcie and the generic SBSA compliant pci
> > implementation.
> 
> You might want to re-read the SBSA. Unless ARM provides an IP block or
> there is some other standard such as EHCI or AHCI, there is no generic
> implementation. You only have to go look at the Linux EHCI or AHCI
> drivers and see how meaningless and inadequate "use EHCI" is. For PCI,
> the text is so brief in the SBSA there will be no way PCI is going to
> just work given all the variations of root complexes, bridges, address
> windows, etc. we typically see on ARM platforms. I could be wrong and
> some AML magic will solve all the problems. :)

The biggest hinderance I've seen while looking at ARM PCI drivers is
quite simply - they don't follow the PCI-E spec. There is a spec, and
it is not followed.

This fixup in the X-Gene is a solid example, the purpose of the BAR in
a PCI-PCI bridge is very clear: using it to specify the system
DRAM aperature is completely wrong.

Not having working aperture windows in the root complex's bridges is
completely wrong.

Lacking any ability to generate 8 and 16 bit config write TLP's is
wrong.

Starting with an end-port PCI-E core and re-tasking it to be a root
port bridge and ignoring all the requirements with the bridge's config
space is utterly and completely WRONG.

Specifying 'use EHCI, AHCI, etc' - which are all PCI based standards
without clearly specifying exactly how PCI is suppose to work is
completely bonkers.

What is needed is a spec that says:
 1) Here is how you generate config TLPs. A MMIO region that
    conforms to the already specified x86 ECAM would
    be perfect
 2) Here is a dword by dword break down of the entire config space in
    a SOC. Here is where a on-board AHCI controller must show up in
    config space. Here is how an external PCI-E port must show
    up. Etc. Most of this is already specified, but it clearly needs
    to be layed out explicitly for ARM SOCs to actually follow it.
 3) Here is how you specify the aperture(s) associated with PCI BAR's
    and bridge windows in config space. And yes: The CONFIG SPACE
    BARS MUST WORK.
 4) Here is how MSI works, these are the values you put in the
    address/data and here is how you collect the interrupt.
 5) Here is how Legacy INTx must be mapped into the GIC.

This is what x86 does, and they have been doing it well for 10
years. If you want to play in the server game you have to properly
implement PCI.

Jason
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