linux-kernel - Re: mips octeon memory model questions

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Message-ID: <20140204193941.GD5002@laptop.programming.kicks-ass.net>
Date:	Tue, 4 Feb 2014 20:39:41 +0100
From:	Peter Zijlstra <peterz@...radead.org>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	David Daney <ddaney@...iumnetworks.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
	linux-mips <linux-mips@...ux-mips.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Paul McKenney <paulmck@...ux.vnet.ibm.com>,
	Will Deacon <will.deacon@....com>
Subject: Re: mips octeon memory model questions

On Tue, Feb 04, 2014 at 11:16:58AM -0800, Linus Torvalds wrote:
> On Tue, Feb 4, 2014 at 11:05 AM, Peter Zijlstra
> >
> >> So writes move down, not up.
> >
> > Right, but the ll-sc store might move down over a later store.
> 
> Unlikely. The thing is, in order for the sc to succeed, it has to
> already have hit the cache coherency domain (or at least reserved it -
> ie maybe the value is not actually *in* the cache, but the sc needs to
> have gotten exclusive access to the cacheline).
> 
> So just how do you expect a later store (that is *after* the
> conditional branch that tests the result of the sc) to move up before
> it?

Ah, I completely overlooked the control dependency to the subsequent
store.

Yes, given that this makes sense.
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