linux-kernel - Re: [PATCH] Convert powerpc simple spinlocks into ticket locks

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Message-Id: <87C29DBB-41E7-4B6C-9089-3C7756FBAE07@kernel.crashing.org>
Date:	Fri, 7 Feb 2014 09:51:16 -0600
From:	Kumar Gala <galak@...nel.crashing.org>
To:	Torsten Duwe <duwe@....de>
Cc:	Scott Wood <scottwood@...escale.com>,
	Tom Musta <tommusta@...il.com>,
	Peter Zijlstra <peterz@...radead.org>,
	linux-kernel@...r.kernel.org, Paul Mackerras <paulus@...ba.org>,
	Anton Blanchard <anton@...ba.org>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	linuxppc-dev@...ts.ozlabs.org, Ingo Molnar <mingo@...nel.org>
Subject: Re: [PATCH] Convert powerpc simple spinlocks into ticket locks


On Feb 7, 2014, at 3:02 AM, Torsten Duwe <duwe@....de> wrote:

> On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
>> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
>>> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
>> 
>>>> Can you pair lwarx with sthcx ? I couldn't immediately find the answer
>>>> in the PowerISA doc. If so I think you can do better by being able to
>>>> atomically load both tickets but only storing the head without affecting
>>>> the tail.
> 
> Can I simply write the half word, without a reservation, or will the HW caches
> mess up the other half? Will it ruin the cache coherency on some (sub)architectures?

The coherency should be fine, I just can’t remember if you’ll lose the reservation by doing this.

>> Plus, sthcx doesn't exist on all PPC chips.
> 
> Which ones are lacking it? Do all have at least a simple 16-bit store?

Everything implements a simple 16-bit store, just not everything implements the store conditional of 16-bit data.

- k--
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