lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 12 Feb 2014 10:02:19 +0000
From:	Lee Jones <lee.jones@...aro.org>
To:	Krzysztof Kozlowski <k.kozlowski@...sung.com>
Cc:	Sangbeom Kim <sbkim73@...sung.com>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	linux-kernel@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
	Kyungmin Park <kyungmin.park@...sung.com>,
	Marek Szyprowski <m.szyprowski@...sung.com>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: [PATCH 05/14] mfd: sec: Use consistent S2MPS11 RTC alarm
 interrupt indexes

On Wed, 12 Feb 2014, Krzysztof Kozlowski wrote:

> On Wed, 2014-02-12 at 09:07 +0000, Lee Jones wrote:
> > > The S2MPS11 RTC has two alarms: alarm0 and alarm1 (corresponding
> > > interrupts are named similarly). Use consistent names for interrupts to
> > > limit possible errors.
> > > 
> > > Signed-off-by: Krzysztof Kozlowski <k.kozlowski@...sung.com>
> > > ---
> > >  drivers/mfd/sec-irq.c           |    8 ++++----
> > >  include/linux/mfd/samsung/irq.h |    4 ++--
> > >  2 files changed, 6 insertions(+), 6 deletions(-)
> > 
> > <snip>
> > 
> > >  #define S2MPS11_IRQ_RTC60S_MASK		(1 << 0)
> > >  #define S2MPS11_IRQ_RTCA1_MASK		(1 << 1)
> > > -#define S2MPS11_IRQ_RTCA2_MASK		(1 << 2)
> > > +#define S2MPS11_IRQ_RTCA0_MASK		(1 << 2)
> > 
> > This doesn't look correct to me.
> 
> It is just renaming RTCA2 to RTCA0 because there is no "alarm 2"
> registers. Actually the behavior of driver does not change (especially
> that there is no RTC driver for S2MPS11) but now it looks properly:
>  - set ALARM0 registers for RTCA0 interrupt,
>  - set ALARM1 registers for RTCA1 interrupt,
> 
> This patch is not essential.

I mean the logic.

If these masks are used for registers then I assume RTCA0 would be
BIT(1) amd RTCA1 would be BIT(2), but this patch swaps them round.

> > >  #define S2MPS11_IRQ_SMPL_MASK		(1 << 3)
> > >  #define S2MPS11_IRQ_RTC1S_MASK		(1 << 4)
> > >  #define S2MPS11_IRQ_WTSR_MASK		(1 << 5)
> > 
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ