linux-kernel - [tip:timers/urgent] tick: Clear broadcast pending bit when switching to oneshot

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Message-ID: <tip-dd5fd9b91a77b4c9c28b7ef9c181b1a875820d0a@git.kernel.org>
Date:	Thu, 13 Feb 2014 12:57:32 -0800
From:	tip-bot for Thomas Gleixner <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	olaf@...fle.de, davej@...hat.com, jwboyer@...hat.com,
	tglx@...utronix.de, pomidorabelisima@...il.com,
	sgruszka@...hat.com, jforbes@...hat.com
Subject: [tip:timers/urgent] tick:
  Clear broadcast pending bit when switching to oneshot

Commit-ID:  dd5fd9b91a77b4c9c28b7ef9c181b1a875820d0a
Gitweb:     http://git.kernel.org/tip/dd5fd9b91a77b4c9c28b7ef9c181b1a875820d0a
Author:     Thomas Gleixner <tglx@...utronix.de>
AuthorDate: Tue, 11 Feb 2014 14:35:40 +0100
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 13 Feb 2014 21:55:54 +0100

tick: Clear broadcast pending bit when switching to oneshot

AMD systems which use the C1E workaround in the amd_e400_idle routine
trigger the WARN_ON_ONCE in the broadcast code when onlining a CPU.

The reason is that the idle routine of those AMD systems switches the
cpu into forced broadcast mode early on before the newly brought up
CPU can switch over to high resolution / NOHZ mode. The timer related
CPU1 bringup looks like this:

  clockevent_register_device(local_apic);
  tick_setup(local_apic);
  ...
  idle()
	tick_broadcast_on_off(FORCE);
	tick_broadcast_oneshot_control(ENTER)
	  cpumask_set(cpu, broadcast_oneshot_mask);
	halt();

Now the broadcast interrupt on CPU0 sets CPU1 in the
broadcast_pending_mask and wakes CPU1. So CPU1 continues:

	local_apic_timer_interrupt()
	   tick_handle_periodic();
	   softirq()
	     tick_init_highres();
	       cpumask_clr(cpu, broadcast_oneshot_mask);

	tick_broadcast_oneshot_control(ENTER)
	   WARN_ON(cpumask_test(cpu, broadcast_pending_mask);

So while we remove CPU1 from the broadcast_oneshot_mask when we switch
over to highres mode, we do not clear the pending bit, which then
triggers the warning when we go back to idle.

The reason why this is only visible on C1E affected AMD systems is
that the other machines enter the deep sleep states via
acpi_idle/intel_idle and exit the broadcast mode before executing the
remote triggered local_apic_timer_interrupt. So the pending bit is
already cleared when the switch over to highres mode is clearing the
oneshot mask.

The solution is simple: Clear the pending bit together with the mask
bit when we switch over to highres mode.

Stanislaw came up independently with the same patch by enforcing the
C1E workaround and debugging the fallout. I picked mine, because mine
has a changelog :)

Reported-by: poma <pomidorabelisima@...il.com>
Debugged-by: Stanislaw Gruszka <sgruszka@...hat.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Olaf Hering <olaf@...fle.de>
Cc: Dave Jones <davej@...hat.com>
Cc: Justin M. Forbes <jforbes@...hat.com>
Cc: Josh Boyer <jwboyer@...hat.com>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1402111434180.21991@ionos.tec.linutronix.de
Cc: stable@...r.kernel.org # 3.10+
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 kernel/time/tick-broadcast.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index 43780ab..98977a5 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -756,6 +756,7 @@ out:
 static void tick_broadcast_clear_oneshot(int cpu)
 {
 	cpumask_clear_cpu(cpu, tick_broadcast_oneshot_mask);
+	cpumask_clear_cpu(cpu, tick_broadcast_pending_mask);
 }

 static void tick_broadcast_init_next_event(struct cpumask *mask,
--
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