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Message-ID: <20140217100221.15040.47203.stgit@pagira.o2s.ch>
Date: Mon, 17 Feb 2014 11:02:21 +0100
From: David Lanzendörfer <david.lanzendoerfer@....ch>
To: devicetree@...r.kernel.org, Ulf Hansson <ulf.hansson@...aro.org>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
Mike Turquette <mturquette@...aro.org>,
Simon Baatz <gmbnomis@...il.com>,
Hans de Goede <hdegoede@...hat.com>,
Emilio López <emilio@...pez.com.ar>,
linux-mmc@...r.kernel.org, Chris Ball <chris@...ntf.net>,
linux-kernel@...r.kernel.org,
H Hartley Sweeten <hsweeten@...ionengravers.com>,
linux-sunxi@...glegroups.com, Tejun Heo <tj@...nel.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Guennadi Liakhovetski <g.liakhovetski@....de>,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v7 2/8] clk: sunxi: Implement MMC phase control
From: Emilio López <emilio@...pez.com.ar>
Signed-off-by: Emilio López <emilio@...pez.com.ar>
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ reg = readl(factors->reg);
+
+ /* set sample clock phase control */
+ reg &= ~(0x7 << 20);
+ reg |= ((sample & 0x7) << 20);
+
+ /* set output clock phase control */
+ reg &= ~(0x7 << 8);
+ reg |= ((output & 0x7) << 8);
+
+ writel(reg, factors->reg);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+}
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
--
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