linux-kernel - [PATCH V4 2/4] ARM: shmobile: r8a7791: Add PCI USB host clock support

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Date:	Sun, 23 Feb 2014 22:00:57 +0400
From:	<vladimir.barinov@...entembedded.com>
To:	<linux-sh@...r.kernel.org>
Cc:	<linus.walleij@...aro.org>, linux-gpio@...r.kernel.org,
	<magnus.damm@...il.com>, <horms@...ge.net.au>, <gnurou@...il.com>,
	<linux-kernel@...r.kernel.org>, <kuninori.morimoto.gx@...esas.com>,
	<valentine.barshak@...entembedded.com>
Subject: [PATCH V4 2/4] ARM: shmobile: r8a7791: Add PCI USB host clock support

From: Vladimir Barinov <vladimir.barinov@...entembedded.com>

This adds internal PCI USB host clock support to R-Car M2 SoC.

Signed-off-by: Valentine Barshak <valentine.barshak@...entembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov@...entembedded.com>

Changes in V4:
Changes in V3:
* none.

Changes in V2:
* capitalized ARM in the subject;
* rebased on top the latest devel tag.

---
 arch/arm/mach-shmobile/clock-r8a7791.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Index: build/arch/arm/mach-shmobile/clock-r8a7791.c
===================================================================
--- build.orig/arch/arm/mach-shmobile/clock-r8a7791.c	2014-02-23 21:47:52.582571801 +0400
+++ build/arch/arm/mach-shmobile/clock-r8a7791.c	2014-02-23 21:47:57.446571701 +0400
@@ -177,7 +177,7 @@
 	MSTP811, MSTP810, MSTP809,
 	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
 	MSTP719, MSTP718, MSTP715, MSTP714,
-	MSTP704,
+	MSTP704, MSTP703,
 	MSTP522,
 	MSTP314, MSTP312, MSTP311,
 	MSTP216, MSTP207, MSTP206,
@@ -210,6 +210,7 @@
 	[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
 	[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
 	[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
+	[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
 	[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
 	[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
 	[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
@@ -285,6 +286,8 @@
 	CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
 	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
 	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
+	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
+	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
 };
 
 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
--
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