linux-kernel - [PATCH v5 0/3] KVM: x86: enable Intel MPX for KVM

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Message-ID: <DE8DF0795D48FD4CA783C40EC82923350150E3B8@SHSMSX101.ccr.corp.intel.com>
Date:	Mon, 24 Feb 2014 10:53:43 +0000
From:	"Liu, Jinsong" <jinsong.liu@...el.com>
To:	'Paolo Bonzini' <pbonzini@...hat.com>,
	"'kvm@...r.kernel.org'" <kvm@...r.kernel.org>,
	"'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>,
	"'qemu-devel@...gnu.org'" <qemu-devel@...gnu.org>
CC:	"'gleb@...hat.com'" <gleb@...hat.com>,
	"'hpa@...or.com'" <hpa@...or.com>
Subject: [PATCH v5 0/3] KVM: x86: enable Intel MPX for KVM

These patches are version 5 to enable Intel MPX for KVM.

Version 1:
  * Add some Intel MPX definiation
  * Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable 
  * vmx and msr handle for MPX support at KVM
  * enalbe MPX feature for guest

Version 2:
  * remove generic MPX definiation, Qiaowei's patch has add the definiation at kernel side
  * add MSR_IA32_BNDCFGS to msrs_to_save

Version 3:
  * rebase on latest kernel, which include Qiaowei's MPX common definiation pulled from HPA's tree

Version 4:
  * Remove xsave bugfix patch from this series as a standalone patch
  * Add a new kvm_x86_ops member mpx_supported, to disable MPX whenever the two VMX controls are not available
  * minor rebase for VMX bit definition

Version 5:
  * Add conditional mpx_supported when expose MPX to guest

Thanks,
Jinsong


Liu Jinsong (3):
  KVM: x86: Intel MPX vmx and msr handle
  KVM: x86: add MSR_IA32_BNDCFGS to msrs_to_save
  KVM: x86: Enable Intel MPX for guest

 arch/x86/include/asm/kvm_host.h       |    1 +
 arch/x86/include/asm/vmx.h            |    4 ++++
 arch/x86/include/uapi/asm/msr-index.h |    1 +
 arch/x86/kvm/cpuid.c                  |    4 +++-
 arch/x86/kvm/vmx.c                    |   24 ++++++++++++++++++++++--
 arch/x86/kvm/x86.c                    |    8 +++++++-
 arch/x86/kvm/x86.h                    |    3 ++-
 7 files changed, 40 insertions(+), 5 deletions(-)
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