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Message-ID: <CADtm3G7JcO6+Sc6Dsw1swY09F7+-KSXjsQU8CBcH-K6On2aP_Q@mail.gmail.com>
Date: Wed, 26 Feb 2014 16:38:20 -0800
From: Gregory Fong <gregory.0xf0@...il.com>
To: Will Deacon <will.deacon@....com>
Cc: Marc Carino <marc.ceeeee@...il.com>,
Christian Daudt <bcm@...thebug.org>,
Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
Florian Fainelli <f.fainelli@...il.com>,
Matt Porter <matt.porter@...aro.org>,
Russell King <linux@....linux.org.uk>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"rob.herring@...xeda.com" <rob.herring@...xeda.com>
Subject: Re: [PATCH v7 5/9] ARM: Enable erratum 798181 for Broadcom Brahma-B15
Hi Will,
On Wed, Feb 26, 2014 at 2:47 AM, Will Deacon <will.deacon@....com> wrote:
> On Wed, Feb 26, 2014 at 10:29:08AM +0000, Marc Carino wrote:
>> From: Gregory Fong <gregory.0xf0@...il.com>
>>
>> Broadcom Brahma-B15 (r0p0..r0p2) is also affected by Cortex-A15
>> erratum 798181, so enable the workaround for Brahma-B15.
>
> Really... *exactly* the same erratum? That sounds pretty unlikely, so I'd
> really like to be sure that the workaround we have indeed solves your
> problem (issuing a dummy TLBI to 0x0 + dsb, then followed by a dmb + clrex
> on each core). The point is that the workaround doesn't simply perform
> non-shareable invalidation on each core using IPIs.
Yes, it should be the same. I've sent you more detail off-list.
Regards,
Gregory
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