linux-kernel - Re: [PATCH v10 1/3] mmc: sdhci-msm: Qualcomm SDHCI binding documentation

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Message-ID: <CAL_JsqKJ5Jn4wb8xtqrc09kkP4dzUA6qDEkK396RW+4qFNVf+Q@mail.gmail.com>
Date:	Wed, 5 Mar 2014 00:56:22 -0600
From:	Rob Herring <robherring2@...il.com>
To:	Georgi Djakov <gdjakov@...sol.com>
Cc:	"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
	Chris Ball <cjb@...top.org>,
	Ulf Hansson <ulf.hansson@...aro.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Stephen Warren <swarren@...dotorg.org>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Rob Landley <rob@...dley.net>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	linux-arm-msm <linux-arm-msm@...r.kernel.org>
Subject: Re: [PATCH v10 1/3] mmc: sdhci-msm: Qualcomm SDHCI binding documentation

On Tue, Mar 4, 2014 at 1:27 PM, Georgi Djakov <gdjakov@...sol.com> wrote:
> This patch adds the device-tree binding documentation for
> Qualcomm SDHCI driver. It contains the differences between
> the core properties in mmc.txt and the properties used by
> the sdhci-msm driver.
>
> Signed-off-by: Georgi Djakov <gdjakov@...sol.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-msm.txt          |   63 ++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> new file mode 100644
> index 0000000..c635c53
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -0,0 +1,63 @@
> +* Qualcomm SDHCI controller (sdhci-msm)
> +
> +This file documents differences between the core properties in mmc.txt
> +and the properties used by the sdhci-msm driver.
> +
> +Required properties:
> +- compatible: Should contain "qcom,sdhci-msm-v4".
> +- reg: Base address and length of the register set listed in reg-names.
> +- reg-names: Should contain the following:
> +       "hc_mem"   - Host controller register map
> +       "core_mem" - SD Core register map

reg-names should not be required and the order specified by the binding.

> +- interrupts: Should contain an interrupt-specifiers for the interrupts listed in interrupt-names.
> +- interrupt-names: Should contain the following:
> +       "hc_irq"     - Host controller interrupt
> +       "pwr_irq"    - PMIC interrupt

Same for interrupt-names.

> +- vdd-supply: Phandle to the regulator for the vdd (core voltage) supply.
> +- vdd-io-supply: Phandle to the regulator for the vdd-io (i/o voltage) supply.
> +- pinctrl-names: Should contain only one value - "default".
> +- pinctrl-0: Should specify pin control groups used for this controller.
> +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
> +- clock-names: Should contain the following:
> +       "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
> +       "core"  - SDC MMC clock (MCLK) (required)
> +       "bus"   - SDCC bus voter clock (optional)
> +
> +Example:
> +
> +       sdhc_1: sdhci@...24900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

Are there cases where these are really in a different 4KB range? If
not, this should just be 1 range.

> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 123 0>, <0 138 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <8>;
> +               non-removable;
> +
> +               vdd-supply = <&pm8941_l20>;
> +               vdd-io-supply = <&pm8941_s3>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
> +
> +               clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> +
> +       sdhc_2: sdhci@...a4900 {
> +               compatible = "qcom,sdhci-msm-v4";
> +               reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> +               reg-names = "hc_mem", "core_mem";
> +               interrupts = <0 125 0>, <0 221 0>;
> +               interrupt-names = "hc_irq", "pwr_irq";
> +               bus-width = <4>;
> +
> +               vdd-supply = <&pm8941_l21>;
> +               vdd-io-supply = <&pm8941_l13>;
> +
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
> +
> +               clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
> +               clock-names = "core", "iface";
> +       };
> --
> 1.7.9.5
>
--
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