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Message-ID: <CABb+yY1y1sOozVU=iAsotWG-q3N=SogjHjZ=iF04CiXF89eeOg@mail.gmail.com>
Date:	Tue, 11 Mar 2014 00:00:12 +0800
From:	Jassi Brar <jassisinghbrar@...il.com>
To:	Srikanth Thokala <sthokal@...inx.com>
Cc:	Dan Williams <dan.j.williams@...el.com>,
	Vinod Koul <vinod.koul@...el.com>, michal.simek@...inx.com,
	grant.likely@...aro.org, robh+dt@...nel.org, levex@...ux.com,
	Lars-Peter Clausen <lars@...afoo.de>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Jaswinder Singh <jaswinder.singh@...aro.org>,
	dmaengine@...r.kernel.org, andriy.shevchenko@...ux.intel.com,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v4 2/2] dma: Add Xilinx AXI Video Direct Memory Access
 Engine driver support

On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala <sthokal@...inx.com> wrote:

> +static struct dma_async_tx_descriptor *
> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
> +                                struct dma_interleaved_template *xt,
> +                                unsigned long flags)
> +{
> +       struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
> +       struct xilinx_vdma_tx_descriptor *desc;
> +       struct xilinx_vdma_tx_segment *segment;
> +       struct xilinx_vdma_tx_segment *prev = NULL;
> +       int i;
> +
> +       if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM))
> +               return NULL;
> +
> +       if (!xt->numf || !xt->sgl[0].size)
> +               return NULL;
> +
> +       /* Allocate a transaction descriptor. */
> +       desc = xilinx_vdma_alloc_tx_descriptor(chan);
> +       if (!desc)
> +               return NULL;
> +
> +       dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
> +       desc->async_tx.tx_submit = xilinx_vdma_tx_submit;
> +       desc->async_tx.cookie = 0;
> +       async_tx_ack(&desc->async_tx);
> +
> +       /* Build the list of transaction segments. */
> +       for (i = 0; i < xt->frame_size; i++) {
> +               struct xilinx_vdma_desc_hw *hw;
> +
> +               /* Allocate the link descriptor from DMA pool */
> +               segment = xilinx_vdma_alloc_tx_segment(chan);
> +               if (!segment)
> +                       goto error;
> +
> +               /* Fill in the hardware descriptor */
> +               hw = &segment->hw;
> +               hw->vsize = xt->numf;
> +               hw->hsize = xt->sgl[0].size;
> +               hw->stride = xt->sgl[0].icg <<
> +                               XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT;
>
It seems the xt->frame_size is (should be?) always going to be 1?
If yes, the for-loop isn't needed.
If no, you should probably use 'i' as the index to sgl[], and not always 0.
--
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