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Date: Wed, 12 Mar 2014 08:16:05 +0100
From: Wolfram Sang <wsa@...-dreams.de>
To: Chew Chiau Ee <chiau.ee.chew@...el.com>
Cc: Mika Westerberg <mika.westerberg@...ux.intel.com>,
Lim Lee Booi <lee.booi.lim@...el.com>,
linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and
SDA hold time value
On Tue, Mar 11, 2014 at 07:33:45PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@...el.com>
>
> On Intel BayTrail, there was case whereby the resulting fast mode
> bus speed becomes slower (~20% slower compared to expected speed)
> if using the HCNT/LCNT calculated in the core layer. Thus, this
> patch is added to allow pci glue layer to pass in optimal
> HCNT/LCNT/SDA hold time values to core layer since the core
> layer supports cofigurable HCNT/LCNT/SDA hold time values now.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@...el.com>
Applied to for-next, thanks!
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