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Date:	Thu, 20 Mar 2014 12:09:00 -0600
From:	Warner Losh <imp@...imp.com>
To:	Santosh Shilimkar <santosh.shilimkar@...com>
Cc:	Brian Norris <computersforpeace@...il.com>,
	Ivan Khoronzhuk <ivan.khoronzhuk@...com>,
	David Woodhouse <dwmw2@...radead.org>, galak@...eaurora.org,
	robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, rob@...dley.net,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	grygorii.strashko@...com, devicetree@...r.kernel.org,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mtd@...ts.infradead.org,
	Murali Karicheri <m-karicheri2@...com>
Subject: Re: [PATCH 2/3] mtd: davinci-nand: add dts property for NAND_NO_SUBPAGE_WRITE option


On Mar 20, 2014, at 12:02 PM, Santosh Shilimkar <santosh.shilimkar@...com> wrote:

> On Thursday 20 March 2014 01:44 PM, Warner Losh wrote:
>> 
>> On Mar 20, 2014, at 11:37 AM, Santosh Shilimkar <santosh.shilimkar@...com> wrote:
>> 
>>> 
>>> 
>>> On Thursday 20 March 2014 01:29 PM, Brian Norris wrote:
>>>> On Thu, Mar 20, 2014 at 01:12:35PM -0400, Santosh Shilimkar wrote:
>>>>> Boris,
>>>> 
>>>> Who's Boris? And why should Boris be taking this patch? It's an MTD
>>>> patch.
>>>> 
>>> I got your name completely wrong. Sorry....
>>> 
>>>>> On Thursday 20 March 2014 01:06 PM, Ivan Khoronzhuk wrote:
>>>>>> From: Murali Karicheri <m-karicheri2@...com>
>>>>>> 
>>>>>> After testing NAND flash with ubifs for k2hk-emv board were committed
>>>>>> that flash doesn't support subpage writing, so we can fix it by
>>>>>> adding a property to disable subpage write.
>>>> 
>>>> What flash? We try to autodetect NAND as much as possible. Perhaps we
>>>> should be adding infrastructure support instead of hacking it with a DT
>>>> property.
>>>> 
>>> We can't auto detect it and thats why the DT approach was taken. We
>>> will double check that.
>> 
>> I though sub page writing was one of the fields in the onfi and/or jedec(toggle) meta data structures. Have you looked there?
>> 
> Am not sure if I follow you. The limitation is from the TI NAND controller(AEMIF) and
> not the NAND memory. 

Then never mind. I thought it was the other side of things.

Warner--
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