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Message-ID: <1943297151.2164.1395472840681.JavaMail.root@bj-mail03.pku.edu.cn>
Date: Sat, 22 Mar 2014 15:20:40 +0800 (CST)
From: 管雪涛 <gxt@....edu.cn>
To: Chen Gang <gang.chen.5i5j@...il.com>
Cc: gxt@...c.pku.edu.cn, linux-kernel@...r.kernel.org,
sunzhichuang <sunzhichuang@...c.pku.edu.cn>
Subject: 回复: [PATCH] arch/unicore32/kernel/clock.c: add readl() and writel() for 'PM_' macros
Thanks Chen.
Cc: Zhichuang Sun <sunzhichuang@...c.pku.edu.cn>
Tested-by: Zhichuang Sun <sunzhichuang@...c.pku.edu.cn>
Acked-by: Xuetao Guan <gxt@....edu.cn>
----- Chen Gang <gang.chen.5i5j@...il.com> 写道:
> Add readl() and writel() for 'PM_' macros, just like another areas have
> done within unicored32, or will cause compiling issue.
>
> The related error (allmodconfig for unicored32):
>
> CC arch/unicore32/kernel/clock.o
> arch/unicore32/kernel/clock.c: In function ‘clk_set_rate’:
> arch/unicore32/kernel/clock.c:182: warning: initialization makes integer from pointer without a cast
> arch/unicore32/kernel/clock.c:204: error: lvalue required as left operand of assignment
> arch/unicore32/kernel/clock.c:206: error: lvalue required as left operand of assignment
> arch/unicore32/kernel/clock.c:207: error: invalid operands to binary & (have ‘void *’ and ‘long unsigned int’)
> make[1]: *** [arch/unicore32/kernel/clock.o] Error 1
> make: *** [arch/unicore32/kernel] Error 2
>
>
> Signed-off-by: Chen Gang <gang.chen.5i5j@...il.com>
> ---
> arch/unicore32/kernel/clock.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/unicore32/kernel/clock.c b/arch/unicore32/kernel/clock.c
> index 18d4563..b1ca775 100644
> --- a/arch/unicore32/kernel/clock.c
> +++ b/arch/unicore32/kernel/clock.c
> @@ -179,7 +179,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
> }
> #ifdef CONFIG_CPU_FREQ
> if (clk == &clk_mclk_clk) {
> - u32 pll_rate, divstatus = PM_DIVSTATUS;
> + u32 pll_rate, divstatus = readl(PM_DIVSTATUS);
> int ret, i;
>
> /* lookup mclk_clk_table */
> @@ -201,10 +201,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
> / (((divstatus & 0x0000f000) >> 12) + 1);
>
> /* set pll sys cfg reg. */
> - PM_PLLSYSCFG = pll_rate;
> + writel(pll_rate, PM_PLLSYSCFG);
>
> - PM_PMCR = PM_PMCR_CFBSYS;
> - while ((PM_PLLDFCDONE & PM_PLLDFCDONE_SYSDFC)
> + writel(PM_PMCR_CFBSYS, PM_PMCR);
> + while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC)
> != PM_PLLDFCDONE_SYSDFC)
> udelay(100);
> /* about 1ms */
> --
> 1.7.9.5
--
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