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Message-ID: <20140327105436.GF30768@sirena.org.uk>
Date: Thu, 27 Mar 2014 10:54:36 +0000
From: Mark Brown <broonie@...nel.org>
To: Nicolin Chen <Guangyu.Chen@...escale.com>
Cc: Xiubo Li-B47053 <Li.Xiubo@...escale.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag
On Thu, Mar 27, 2014 at 11:57:27AM +0800, Nicolin Chen wrote:
> On Thu, Mar 27, 2014 at 12:06:53PM +0800, Xiubo Li-B47053 wrote:
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are all the
> > Same as above, and nothing else.
> > Have I missed ?
> What i.MX IC team told me is SAI ignores what we do to FWF and FRF, so you
> don't need to worry about it at all unless Vybrid makes them writable, in
> which case we may also need to clear these bits and confirm with Vybrid IC
> team if they're also W1C.
And even if it payed attention I'd expect that a lot of the time they'd
just be reasserted immediately as the condition still holds.
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