linux-kernel - RE: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag

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Message-ID: <d77b7d1800884badbdb50564b8460267@BY2PR03MB505.namprd03.prod.outlook.com>
Date:	Thu, 27 Mar 2014 04:18:27 +0000
From:	"Li.Xiubo@...escale.com" <Li.Xiubo@...escale.com>
To:	"guangyu.chen@...escale.com" <guangyu.chen@...escale.com>
CC:	"broonie@...nel.org" <broonie@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: RE: [PATCH] ASoC: fsl_sai: Add isr to deal with error flag

> > So let's just ignore the clearance of these bits in isr().
> >
> > +++++
> > SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : 0000_0000h
> 
> I'm talking about FWF and FRF bits, not TCSR as a register.
> 
> > -----
> >
> > I have checked in the Vybrid and LS1 SoC datasheets, and they are all the
> > Same as above, and nothing else.
> >
> > Have I missed ?
> 
> What i.MX IC team told me is SAI ignores what we do to FWF and FRF, so you
> don't need to worry about it at all unless Vybrid makes them writable, in
> which case we may also need to clear these bits and confirm with Vybrid IC
> team if they're also W1C.
> 

Well, if so, that's fine.

Thanks,
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