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Message-Id: <1396350948-29910-115-git-send-email-luis.henriques@canonical.com>
Date: Tue, 1 Apr 2014 12:15:18 +0100
From: Luis Henriques <luis.henriques@...onical.com>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org,
kernel-team@...ts.ubuntu.com
Cc: Stefan Agner <stefan@...er.ch>, daniel.lezcano@...aro.org,
linux-arm-kernel@...ts.infradead.org, linux@....linux.org.uk,
Thomas Gleixner <tglx@...utronix.de>,
Luis Henriques <luis.henriques@...onical.com>
Subject: [PATCH 3.11 114/144] clocksource: vf_pit_timer: use complement for sched_clock reading
3.11.10.7 -stable review patch. If anyone has any objections, please let me know.
------------------
From: Stefan Agner <stefan@...er.ch>
commit 224aa3ed45c8735ae02bb2ecca002409fa6aa772 upstream.
Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.
Signed-off-by: Stefan Agner <stefan@...er.ch>
Acked-by: Shawn Guo <shawn.guo@...aro.org>
Cc: daniel.lezcano@...aro.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux@....linux.org.uk
Link: http://lkml.kernel.org/r/d25af915993aec1b486be653eb86f748ddef54fe.1394057313.git.stefan@agner.ch
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Signed-off-by: Luis Henriques <luis.henriques@...onical.com>
---
drivers/clocksource/vf_pit_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
index 587e020..e559095 100644
--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
static unsigned int pit_read_sched_clock(void)
{
- return __raw_readl(clksrc_base + PITCVAL);
+ return ~__raw_readl(clksrc_base + PITCVAL);
}
static int __init pit_clocksource_init(unsigned long rate)
--
1.9.1
--
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