/* * Device Tree Generator version: 1.1 * * (C) Copyright 2007-2013 Xilinx, Inc. * (C) Copyright 2007-2013 Michal Simek * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd * * Michal SIMEK * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 2013.3 EDK_P.20131013 * Today is: Thursday, the 21 of November, 2013; 19:47:51 * * XPS project directory: . */ /dts-v1/; / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,microblaze"; hard-reset-gpios = <&reset_gpio 0 1>; model = "."; aliases { ethernet0 = &axi_ethernet_eth_buf; serial0 = &rs232_uart; } ; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; linux,stdout-path = "/axi@0/serial@40400000"; } ; cpus { #address-cells = <1>; #cpus = <0x1>; #size-cells = <0>; microblaze_0: cpu@0 { bus-handle = <µblaze_0_axi_periph_xbar>; clock-frequency = <100000000>; compatible = "xlnx,microblaze-9.2"; d-cache-baseaddr = <0x80000000>; d-cache-highaddr = <0xbfffffff>; d-cache-line-size = <0x20>; d-cache-size = <0x4000>; device_type = "cpu"; i-cache-baseaddr = <0x80000000>; i-cache-highaddr = <0xbfffffff>; i-cache-line-size = <0x10>; i-cache-size = <0x4000>; interrupt-handle = <µblaze_0_axi_intc>; model = "microblaze,9.2"; reg = <0>; timebase-frequency = <100000000>; xlnx,addr-tag-bits = <0x10>; xlnx,allow-dcache-wr = <0x1>; xlnx,allow-icache-wr = <0x1>; xlnx,area-optimized = <0x0>; xlnx,async-interrupt = <0x1>; xlnx,avoid-primitives = <0x0>; xlnx,base-vectors = <0x0>; xlnx,branch-target-cache-size = <0x0>; xlnx,cache-byte-size = <0x4000>; xlnx,d-axi = <0x1>; xlnx,d-lmb = <0x1>; xlnx,data-size = <0x20>; xlnx,dcache-addr-tag = <0x10>; xlnx,dcache-always-used = <0x1>; xlnx,dcache-byte-size = <0x4000>; xlnx,dcache-data-width = <0x0>; xlnx,dcache-force-tag-lutram = <0x0>; xlnx,dcache-line-len = <0x8>; xlnx,dcache-use-writeback = <0x1>; xlnx,dcache-victims = <0x0>; xlnx,debug-enabled = <0x1>; xlnx,div-zero-exception = <0x1>; xlnx,dynamic-bus-sizing = <0x0>; xlnx,ecc-use-ce-exception = <0x0>; xlnx,edge-is-positive = <0x0>; xlnx,enable-discrete-ports = <0x0>; xlnx,endianness = <0x1>; xlnx,fault-tolerant = <0x0>; xlnx,fpu-exception = <0x0>; xlnx,freq = <0x5f5e100>; xlnx,fsl-exception = <0x0>; xlnx,fsl-links = <0x0>; xlnx,i-axi = <0x0>; xlnx,i-lmb = <0x1>; xlnx,icache-always-used = <0x1>; xlnx,icache-data-width = <0x0>; xlnx,icache-force-tag-lutram = <0x0>; xlnx,icache-line-len = <0x4>; xlnx,icache-streams = <0x1>; xlnx,icache-victims = <0x8>; xlnx,ill-opcode-exception = <0x1>; xlnx,instance = "kc705_microblaze_0_0"; xlnx,interconnect = <0x2>; xlnx,interrupt-is-edge = <0x0>; xlnx,lockstep-select = <0x0>; xlnx,lockstep-slave = <0x0>; xlnx,mmu-dtlb-size = <0x4>; xlnx,mmu-itlb-size = <0x2>; xlnx,mmu-privileged-instr = <0x0>; xlnx,mmu-tlb-access = <0x3>; xlnx,mmu-zones = <0x2>; xlnx,number-of-pc-brk = <0x1>; xlnx,number-of-rd-addr-brk = <0x0>; xlnx,number-of-wr-addr-brk = <0x0>; xlnx,opcode-0x0-illegal = <0x1>; xlnx,optimization = <0x0>; xlnx,pc-width = <0x20>; xlnx,pvr = <0x2>; xlnx,pvr-user1 = <0x0>; xlnx,pvr-user2 = <0x0>; xlnx,reset-msr = <0x0>; xlnx,sco = <0x0>; xlnx,trace = <0x0>; xlnx,unaligned-exceptions = <0x1>; xlnx,use-barrel = <0x1>; xlnx,use-branch-target-cache = <0x1>; xlnx,use-config-reset = <0x0>; xlnx,use-dcache = <0x1>; xlnx,use-div = <0x1>; xlnx,use-ext-brk = <0x0>; xlnx,use-ext-nm-brk = <0x0>; xlnx,use-extended-fsl-instr = <0x0>; xlnx,use-fpu = <0x0>; xlnx,use-hw-mul = <0x2>; xlnx,use-icache = <0x1>; xlnx,use-interrupt = <0x2>; xlnx,use-mmu = <0x3>; xlnx,use-msr-instr = <0x1>; xlnx,use-pcmp-instr = <0x1>; xlnx,use-reorder-instr = <0x1>; xlnx,use-stack-protection = <0x0>; } ; } ; ddr3_sdram: memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; } ; microblaze_0_axi_periph_xbar: axi@0 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,axi-crossbar-2.1", "simple-bus"; ranges ; axi_ethernet_dma: axi-dma@41e00000 { axistream-connected = <&axi_ethernet_eth_buf>; axistream-control-connected = <&axi_ethernet_eth_buf>; compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a"; interrupt-parent = <µblaze_0_axi_intc>; interrupts = <2 2>, <3 2>; reg = <0x41e00000 0x10000>; xlnx,dlytmr-resolution = <0x7d>; xlnx,enable-multi-channel = <0x0>; xlnx,include-mm2s = <0x1>; xlnx,include-mm2s-dre = <0x1>; xlnx,include-mm2s-sf = <0x1>; xlnx,include-s2mm = <0x1>; xlnx,include-s2mm-dre = <0x1>; xlnx,include-s2mm-sf = <0x1>; xlnx,include-sg = <0x1>; xlnx,micro-dma = <0x0>; xlnx,mm2s-burst-size = <0x10>; xlnx,num-mm2s-channels = <0x1>; xlnx,num-s2mm-channels = <0x1>; xlnx,prmry-is-aclk-async = <0x0>; xlnx,s2mm-burst-size = <0x10>; xlnx,sg-include-stscntrl-strm = <0x1>; xlnx,sg-length-width = <0xe>; xlnx,sg-use-stsapp-length = <0x1>; } ; axi_ethernet_eth_buf: axi-ethernet@44a00000 { axistream-connected = <&axi_ethernet_dma>; axistream-control-connected = <&axi_ethernet_dma>; clock-frequency = <100000000>; compatible = "xlnx,axi-ethernet-buffer-2.0", "xlnx,axi-ethernet-1.00.a"; device_type = "network"; interrupt-parent = <µblaze_0_axi_intc>; interrupts = <1 2>; local-mac-address = [ 00 0a 35 00 42 4a ]; phy-handle = <&phy0>; reg = <0x44a00000 0x40000>; xlnx,avb = <0x0>; xlnx,halfdup = "1"; xlnx,include-io = "1"; xlnx,mcast-extend = <0x0>; xlnx,phy-type = <0x1>; xlnx,phyaddr = <0x1>; xlnx,rxcsum = <0x0>; xlnx,rxmem = <0x1000>; xlnx,rxvlan-strp = <0x0>; xlnx,rxvlan-tag = <0x0>; xlnx,rxvlan-tran = <0x0>; xlnx,stats = <0x0>; xlnx,txcsum = <0x0>; xlnx,txmem = <0x1000>; xlnx,txvlan-strp = <0x0>; xlnx,txvlan-tag = <0x0>; xlnx,txvlan-tran = <0x0>; xlnx,type = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { compatible = "marvell,88e1111"; device_type = "ethernet-phy"; reg = <7>; } ; } ; } ; axi_timer_0: system-timer@41c00000 { clock-frequency = <100000000>; compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; interrupt-parent = <µblaze_0_axi_intc>; interrupts = <0 2>; reg = <0x41c00000 0x10000>; xlnx,count-width = <0x20>; xlnx,gen0-assert = <0x1>; xlnx,gen1-assert = <0x1>; xlnx,one-timer-only = <0x0>; xlnx,trig0-assert = <0x1>; xlnx,trig1-assert = <0x1>; } ; dip_switches_4bits: gpio@40010000 { #gpio-cells = <2>; compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x40010000 0x10000>; xlnx,all-inputs = <0x1>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x0>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x0>; xlnx,dout-default-2 = <0x0>; xlnx,gpio-width = <0x4>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xffffffff>; xlnx,tri-default-2 = <0xffffffff>; } ; led_8bits: gpio@40020000 { #gpio-cells = <2>; compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x40020000 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x0>; xlnx,dout-default-2 = <0x0>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xffffffff>; xlnx,tri-default-2 = <0xffffffff>; } ; microblaze_0_axi_intc: interrupt-controller@41200000 { #interrupt-cells = <0x2>; compatible = "xlnx,axi-intc-4.0", "xlnx,xps-intc-1.00.a"; interrupt-controller ; reg = <0x41200000 0x10000>; xlnx,kind-of-intr = <0x0>; xlnx,num-intr-inputs = <0x5>; } ; primary_flash: flash@60000000 { #address-cells = <1>; #size-cells = <1>; bank-width = <2>; compatible = "xlnx,axi-emc-2.0", "cfi-flash"; reg = <0x60000000 0x8000000>; xlnx,axi-clk-period-ps = <0x2710>; xlnx,include-datawidth-matching-0 = <0x1>; xlnx,include-datawidth-matching-1 = <0x1>; xlnx,include-datawidth-matching-2 = <0x1>; xlnx,include-datawidth-matching-3 = <0x1>; xlnx,include-negedge-ioregs = <0x0>; xlnx,instance = "axi_emc_inst"; xlnx,lflash-period-ps = <0x4e20>; xlnx,linear-flash-sync-burst = <0x0>; xlnx,max-mem-width = <0x10>; xlnx,mem0-type = <0x2>; xlnx,mem0-width = <0x10>; xlnx,mem1-type = <0x2>; xlnx,mem1-width = <0x10>; xlnx,mem2-type = <0x2>; xlnx,mem2-width = <0x10>; xlnx,mem3-type = <0x2>; xlnx,mem3-width = <0x10>; xlnx,num-banks-mem = <0x1>; xlnx,parity-type-mem-0 = <0x0>; xlnx,parity-type-mem-1 = <0x0>; xlnx,parity-type-mem-2 = <0x0>; xlnx,parity-type-mem-3 = <0x0>; xlnx,s-axi-en-reg = <0x0>; xlnx,s-axi-mem-addr-width = <0x20>; xlnx,s-axi-mem-data-width = <0x20>; xlnx,s-axi-mem-id-width = <0x1>; xlnx,s-axi-reg-addr-width = <0x5>; xlnx,s-axi-reg-data-width = <0x20>; xlnx,synch-pipedelay-0 = <0x1>; xlnx,synch-pipedelay-1 = <0x1>; xlnx,synch-pipedelay-2 = <0x1>; xlnx,synch-pipedelay-3 = <0x1>; xlnx,tavdv-ps-mem-0 = <0x1fbd0>; xlnx,tavdv-ps-mem-1 = <0x3a98>; xlnx,tavdv-ps-mem-2 = <0x3a98>; xlnx,tavdv-ps-mem-3 = <0x3a98>; xlnx,tcedv-ps-mem-0 = <0x1fbd0>; xlnx,tcedv-ps-mem-1 = <0x3a98>; xlnx,tcedv-ps-mem-2 = <0x3a98>; xlnx,tcedv-ps-mem-3 = <0x3a98>; xlnx,thzce-ps-mem-0 = <0x1b58>; xlnx,thzce-ps-mem-1 = <0x1b58>; xlnx,thzce-ps-mem-2 = <0x1b58>; xlnx,thzce-ps-mem-3 = <0x1b58>; xlnx,thzoe-ps-mem-0 = <0x1b58>; xlnx,thzoe-ps-mem-1 = <0x1b58>; xlnx,thzoe-ps-mem-2 = <0x1b58>; xlnx,thzoe-ps-mem-3 = <0x1b58>; xlnx,tlzwe-ps-mem-0 = <0xc350>; xlnx,tlzwe-ps-mem-1 = <0x0>; xlnx,tlzwe-ps-mem-2 = <0x0>; xlnx,tlzwe-ps-mem-3 = <0x0>; xlnx,tpacc-ps-flash-0 = <0x61a8>; xlnx,tpacc-ps-flash-1 = <0x61a8>; xlnx,tpacc-ps-flash-2 = <0x61a8>; xlnx,tpacc-ps-flash-3 = <0x61a8>; xlnx,twc-ps-mem-0 = <0x3a98>; xlnx,twc-ps-mem-1 = <0x3a98>; xlnx,twc-ps-mem-2 = <0x3a98>; xlnx,twc-ps-mem-3 = <0x3a98>; xlnx,twp-ps-mem-0 = <0x13880>; xlnx,twp-ps-mem-1 = <0x2ee0>; xlnx,twp-ps-mem-2 = <0x2ee0>; xlnx,twp-ps-mem-3 = <0x2ee0>; xlnx,twph-ps-mem-0 = <0x13880>; xlnx,twph-ps-mem-1 = <0x2ee0>; xlnx,twph-ps-mem-2 = <0x2ee0>; xlnx,twph-ps-mem-3 = <0x2ee0>; xlnx,wr-rec-time-mem-0 = <0x186a0>; xlnx,wr-rec-time-mem-1 = <0x6978>; xlnx,wr-rec-time-mem-2 = <0x6978>; xlnx,wr-rec-time-mem-3 = <0x6978>; partition@0x00000000 { label = "fpga"; reg = <0x00000000 0x00b00000>; }; partition@0x00b00000 { label = "boot"; reg = <0x00b00000 0x00040000>; }; partition@0x00b40000 { label = "bootenv"; reg = <0x00b40000 0x00020000>; }; partition@0x00b60000 { label = "image"; reg = <0x00b60000 0x00c00000>; }; partition@0x01760000 { label = "spare"; reg = <0x01760000 0x00000000>; }; } ; push_buttons_5bits: gpio@40030000 { #gpio-cells = <2>; compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x40030000 0x10000>; xlnx,all-inputs = <0x1>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x0>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x0>; xlnx,dout-default-2 = <0x0>; xlnx,gpio-width = <0x5>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xffffffff>; xlnx,tri-default-2 = <0xffffffff>; } ; reset_gpio: gpio@40000000 { #gpio-cells = <2>; compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x40000000 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x0>; xlnx,dout-default-2 = <0x0>; xlnx,gpio-width = <0x1>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xffffffff>; xlnx,tri-default-2 = <0xffffffff>; } ; rs232_uart: serial@40400000 { clock-frequency = <100000000>; compatible = "xlnx,axi-uart16550-2.0", "xlnx,xps-uart16550-2.00.a", "ns16550a"; current-speed = <115200>; device_type = "serial"; interrupt-parent = <µblaze_0_axi_intc>; interrupts = <4 2>; reg = <0x40400000 0x2000>; reg-offset = <0x1000>; reg-shift = <2>; xlnx,external-xin-clk-hz = <0x17d7840>; xlnx,external-xin-clk-hz-d = <0x19>; xlnx,has-external-rclk = <0x0>; xlnx,has-external-xin = <0x0>; xlnx,is-a-16550 = <0x1>; xlnx,s-axi-aclk-freq-hz-d = <0x64>; xlnx,use-modem-ports = <0x1>; xlnx,use-user-ports = <0x1>; } ; } ; } ;