linux-kernel - Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming

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Date:	Fri, 04 Apr 2014 09:55:51 -0600
From:	Stephen Warren <swarren@...dotorg.org>
To:	Thierry Reding <treding@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	Prashant Gaikwad <pgaikwad@...dia.com>
CC:	linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming

On 04/04/2014 07:55 AM, Thierry Reding wrote:
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
> lowest bits of the register. This lead to a situation where the PLLE
> programming would only work if the register hadn't been touched before.

The series,
Acked-by: Stephen Warren <swarren@...dia.com>

(I might have squashed patches 1 and 2 together, but no matter)

I expect these patches should be CC: stable when applied?
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